CoreSight Trace Memory Controller (TMC) support

Hard real-time debugging requires close interaction with the processor. Tracing shall provide a chronological picture of a system inner working up to, starting from or in the vicinity an event, mainly to guide a human in understanding a faulty program. TMC was defined for this purpose and is available on the Arm derivatives.

CoreSight Trace Memory Controller

CoreSight Trace Memory Controller (TMC) extends the CoreSight Embedded Trace Buffer (ETB) with Embedded Trace FIFO (ETF) and Embedded Trace Router (ETR). It can be used to capture trace using a 2-pin serial wire debug (SWD) and the system memory as dynamic Random Access Memory (RAM). TMC is available on some Arm Cortex-R52 derivatives and supported by Universal Debug Engine.

The  Universal Debug Engine supports TMC as well as the external trace mechanism. There is no additional hardware required.

Architectures