Cortex-A72 Jacinto™ 7 TDA4 and DRA8 SoC family from Texas Instruments

The Arm® Cortex®-A72 based Jacinto™ 7 processors TDA4 and DRA8 are highly integrated processors designed for next-generation of ADAS and gateway applications.

The TDA4 family is targeting ADAS and autonomous vehicle (AV) applications.

Key Features

Dual 64-bit Arm® Cortex®-A72 microprocessor subsystem at up to 2.0 GHz
Six Arm® Cortex®-R5F MCUs at up to 1.0 GHz
Embedded MultiMediaCard Interface ( eMMC)
Two simultaneous flash interfaces configured as
- One OSPI and one QSPI flash interfaces
- or one HyperBus™ and one QSPI flash interface

The DRA8 family is optimized for gateway systems with cloud connectivity.

Key Features

Dual 64-bit Arm® Cortex®-A72 microprocessor subsystem at up to 2.0 GHz
4× Arm® Cortex®-R5F MCUs at up to 1.0 GHz with optional lockstep operation
Embedded MultiMediaCard Interface ( eMMC)
One Octal SPI / Xccela™ / HyperBus™ Memory Controller (HBMC) interface

UDE - Universal Debug Engine for Jacinto™ 7 TDA4 and DRA8 SoC family

UDE - Universal Debug Engine - is a flexible debug and test platform for multi-core debugging of the Texas Instruments Jacinto™ 7 TDA4 and DRA8.

UDE Key Features for TDA4 and DRA8

Multicore debugging
- In one common debugger environment
- Synchronized run-control
- Multicore breakpoints
Core support
- Armv8-A 64 bit instruction set
- Cortex-R
- Device Management Security Controller (DMSC), if debugging is not blocked
FLASH programming