UDE® Release Notes

Changes from 2025.2 to 2025.3 (29.09.2025)

New Features

Enhanced support of TC4x (Infineon) derivatives.
Support of STM32C5xx series from ST Microelectronics.
Support of TI AM2643 from Texas Instruments.
Support of GD32A711/712 B step from GigaDevice.
Support of TLE9954 from Infineon.
Traveo T2G: Support for setting lifecycle modes.
Traveo T2G: Setting StackPointer of CM7 slave core to target interface options added.
Cortex: Setting pin option to target interface added.
Support for Green Hills RISC-V compiler added.
Support for SDCC XC800 compiler added.
µC/OS-II : Extend stack utilization by limit pattern.
Challenge/response connect for S32G3.
Application note for challenge/response connect for S32xxx.
SR6G6: update register database.
SR6G7: update register database.
SR6P6: update register database.
SR6P3: update register database.
SR6P7: update register database.
GD32A7: update register database.
Create NVR restoring script for FC3700 from Flagchip.
XCP/SR6x: Workaround for UDE connect not possible with FETK-T4 and HSP 14.5.0.
Use local path for symbol database by default.
AURIX: simplify access to COMDATA via automation interfaces.
Enhanced support for Infineon's Automotive RISC-V Prototype running on Synopsys Virtualizer Studio platform.
Automatically detect 'running on server' use case.
Support for external FLASH type MX29F800CT-B.
VC runtime package updated to 14.44.35211.
Python support for executing scripts defined in the UDE target configuration.

Bugfixes

Code Coverage: Enhance detection of invalid CFI.
Code Coverage: No Sourcelines in View and Report with very large applications fixed.
UDESim SR6P6: Handling of NaN signs.
UDESim SR6P6: Invalid handling of sign and NaN instruction for VDIV instruction.
Crash when loading ELF File with very long demangled C++ name fixed.
No source code display for RAM code (Green Hills V800 compiler) fixed.
Handling of path segments "\\..\\" in source file pathes fixed.
Improving sorting and filtering of line symbols in compiler add-ins CAIGHSRISCV, GAIGNUTC, CAIGHSTC.
S32G399: Handling of misaligned addresses.
Enabling RH850/U2A6 ICUM core via option bytes not possible.
TC3xx: HSM sector protection not working with SOTA alternate mapping.
TC3xx: improve connect with locked HSM.
Provide asynchronous update of Python Script Console.

Changes from 2025.1 to 2025.2 (04.07.2025)

New Features

Enhanced support of TC4x (Infineon) derivatives.
Support of new devices from Flagchip: FC7240F2MDS, FC7300F8MDQ, FC4150F1MB.
STM32H5xx series support.
SR6: Implement support for low power states.
Support for C3008 A/B bank switch.
C*Core Password unlock not available.
Implement support for TEU_GRM in RH850/C1M-A2.
AURIX: optionally reset SCR on connect/reset.
Python-Add-In: Python 3.12.11 updated.
Python-Add-In: Toolbar buttons possible.
Python-Add-In: Watches dialog available.
Support of Keil C compiler for 8051.
Stack High Water Mark Implementation for ARTI.
µC/OS-II: Stack Utilization.
Indicate *.hpp files for syntax highlighting.
ETMV4 check power up state on Start trace.
Register database updates: TC4, STM32H5, CCFC3007, CCFC3008.
VC runtime package updated to 14.44.35208.

Bugfixes

PXROS-HR update on target hold does not work.
ARM Disassembler - several bugfixes and enhancements.
The integrated ARM assembler should resolve NOP to NOP machine code instead to MOV R8, R8 machine code.
Locals not visible in certain functions (GHS PPC).
Wrong value of local variable (IAR/ARM compiler).
No fixed address variables are visible in symbol browser (Tasking XC800).
Locals have no location in certain functions (HighTec TriCore LLVM).
No SWD default target configuration for TRAVEO T2G CYT6B.
FreeRTOS Task tab not updated on break and target reset.
RH850 failed to start trace if core is disabled.
UAD2proV2/UAD2next Firmware: Connection to UAD lost when loading program via inactive HSM.
RH850/U2B-E: setting breakpoints while runnning not possible in cyclic run mode.
Invalid code disassembly shown after reload with changed content.
UDE/Tessy: hang-up on reload.
TC2: breakpoint can't be set at source line.
AURIX: improve handling of broken reset signal.

Changes from 2025.0.5 to 2025.1 (30.04.2025)

New Features

Enhanced support of TC4x (Infineon) derivatives.
Support of new member of Automotive R-Car family from Renesas.
AURIX TC2xx/TC3xx Trace: Option to use timestamps instead of ticks to save on-chip trace memory.
Python-Add-In: Python 3.12.10 updated.
PowerPc debugging: Update derivatives for C*Core CCFC3007 and CCFC3008.
AURIX SCR debugging: Allow to reconnect SCR without reset.

Bugfixes

Call Graph: Improve recursion detection on static graph export to text file.
PowerPc debugging: Update derivatives for C*Core CCFC3007 and CCFC3008.
Fixed PTM enabling after KeepRunning connect.
AURIX SCR debugging: Allow to reconnect SCR without reset.
Profiling (Stats) - IP trace wont start on fresh opened Workspace.
TC38x: remove non-responsive DOM0 registers for display.
SFR-Window: CTRL + Click for deselect not working in Browse Dialog.
TC4Dx: FilterMemAcc wrong at 0x82000000.
Regression: RH850/P1M connect not possible.

Changes from 2025.0.4 to 2025.0.5 (04.04.2025)

New Features

Cortex M debugging: GD32A7xxx trace support added.
Cortex M debugging: THA6412 debug and trace added.
Cortex M debugging: Basic support for NS800RT3025/NS800RT5039/NS800RT5049 from Novosense.
Support of AM263P4 from Texas Instruments.
Support of external OctoSPI FLASH on AM263P4.
Infineon's Automotive RISC-V Prototype running on Synopsys Virtualizer Studio platform supported.
Simulated I/O supported on RH850 devices from Renesas.
Profiling: Import and Export predefined ranges from/to file.
Enhanced support of TC4x (Infineon) derivatives.
Support of COSIDE(R) GTM simulation model from company COSEDA.
Support of AURIX based ECU's from TTControl.
Execution Sequence: Improve user guidance on function flow.
Execution Sequence: Track the active function of a task.
Execution Sequence: Navigate easily to prev / next function.
Traveo II CYT2xx Register databases updated.
Enhanced filter for search in preconfigured target files.
Simulate 'SSW wait...' function in AURIX/HSM configurations.
AURIX/SCR: improve connection failed report.
ARC/CTRX: Add 51/59 bit and MPLL 172 bit TCU register accesses.
AURIX/MCDS: Use timestamps as ticks to save trace memory.
VC runtime package updated to 14.42.34438.

Bugfixes

Cortex M debugging: Fixed multicore run control for GD32A7xxx.
Profiling: Fix automatic range (top and bottom) and pre-defined range handling.
Profiling: Fix hotkeys usage in pre-defined range list.
Profiling: Fix crash with pre-defined range list, when no samples are available.
Code Coverage: Symbol browser should not show inline functions.
Global Time: Fix synchronization for trace based analyses.
Filter for default target configuration file improved.
AURIX: Suspend not working on halt after external reset.
ORTI Parser does not support unsigned integer format 0U.
Code Coverage - Symbol browser should not show inline functions.
ARC/CTRX: Enable Clock in Sleep Mode not done in Break/KeepApplicationRunning Connect.
Profiling (Stats) - Crash sometimes when using ranges.
Profiling (stats) - Improve Help File.
No bitfield detection with DWARF 4 debug info.
Call Graph - CSV and MRG export should use semicolon.
Profiling - User defined ranges disappear in Pre-Defined Range Mode.

Changes from 2025.0.3 to 2025.0.4 (31.01.2025)

New Features

Python-Add-In: Python 3.12.7 updated.
RH850: Support for RH850/U2B GTM trace added.
Cortex Debugging: Support for MSPM0 G-Series MSPM0G350x and MSPM0G351x added.
GD32A7 (GigaDevice) Basic debug support.
CCFC3012PT (C*Core) debug and trace support.
S32K36x (NXP) debug and trace support.
Enhanced support of TC4x (Infineon) derivatives.
External FLASH GD25LX512ME (GigaDevice) supported at S32G.
TC38x (Infineon) miniMCDS OLDA trace supported.
Execution Sequence Chart: Navigate to code at time.
Execution Sequence Chart: Search for function name.
Trace: Use UDE® program name in default path for temporary decoded trace.
Trace: Add property page for general trace settings.
UEC: Add PPU trace to TC4x UEC configuration.
eMMC programming in UDE® user interface.
C++ support for GHS RH850 compiler.
RH850 JTAG connection supported also with UAD3+.
UDE® Automation application notes updated.
Active core highlighted in toolbar core box.
AURIX™ (Infineon) UCB dialogs: Improve Read/UpdateStatus functions.
Filter for default target configuration file selection.
Support 'target walk-able stack' build option (-gtws) for callstack display GHS RH850.
VC runtime package updated to 14.42.34433.

Bugfixes

RH850: Fixed ignored RH850 option bytes settings.
ORTI Trace Cat2ISR display is not correct.
Code Coverage: Fix invalid branch coverage in ARM targets.
UDE® Sim: Fix interrupt implementation in SR6P6 target.
UDE® Sim: Fix implementation of VCVT instructions.
UDEVisualPlatform and UDEDesktop: Fix crash when opening Peripherals Browser.
RH850 GHS callstack shows wrong sequence (build without -gtws option).
In one certain function parameters and locals are missed in Locals window (GHS 2022).
Show inlined function name instead of surrounded outer global function during pointer resolution.
Symbol resolution in call stack window works only for program @1.
Make error messages to info messages for missing MCDS license.
PXROS-HR window shows invalid expressions fixed.
RH850 U2B ICUP flash driver initialization failed with UAD3+.
License check option for current used target interface can be lost.
ARM: Decode thumb instructions depending on previous IT instructions.
S32K3 Data Flash issue with HSE Firmware enabled.
SR6P3: TCM filter for inactive cores is wrong for Core10.
SR6 debugging via XCP: TCM mapping not working.
SR6: Trigger setup dialog is not working anymore.
New SFR-Window: Crash when pressing Ctrl+C fixed.
Traveo II: Calculating wrong PLL value when using PLL400Mx.
Traveo II / XMC7xxx: Modify flash driver to run on all CM7 slave cores.
XMC7000: Improve CM7 halt-after-reset behavior.
THA6206 flash driver: AArch32 drivers are not compatible to Thumb start mode.
THA6xxx: Flash programming not possible when programming over row borders.
TC4x: connect not working with CS in foreground boot mode.
Breakpoint is set to wrong address fixed - GHS ARM.
Breakpoint is set to wrong address fixed - Diab PPC.
UDE® Memtool: potential hang-up in batch mode fixed.

Changes from 2025.0.2 to 2025.0.3 (11.10.2024)

New Features

Cortex Debugging: Support for Tongxin THA6206 added.
Cortex Debugging: Support for NXP S32K310 added.
Cortex Debugging: Support for STM SR6G6 added.
Register database updates: SR6G7, SR6P3, SR6P6, SR5E.
Cortex Debugging: Added statistical profiling for Cortex AV8 targets.
Support debugging of TC4D production devices.
Update RH850 register databases with bitfield infos.
Update UDE® support for TESSY from Razorcat.
RH850 U2B ICU trace.
RH850 F1KM-S1 trace.
TSim: add MemInit command.
S32G: Create serial RCON script for programming I2C EEPROM.
S32G: Create eMMC script for programming external NAND memory.
TC49xN support.
RH850 F1KH-D8/F1KM-S4 ICU support.
TC49xN (ARC): Initial PPU and CDSP debug support.
SR6G6 16M support.
TC3 HSM: SOTA support.
Support of RTOS Sciopta on XMC4500.
New ARM floating point register schema for GHS DWARF2 information.
Executions Sequence Chart: Navigate to code at time.
TC4x: Dual-MCDS cross trigger routing.
TC4x: State machine support for dual MCDS.
Improved and more convenient lists for initialization commands.
SimplyTrace® for RH850 targets.
Support 128-bit values from HighTec's Rust compiler.
New UDE® Welcome page.
RH850 Trace: Support Sequencer of Trigger Event Unit.
THA6206: Initial DFLASH NVR UCB programming added.
THA6206: SFLASH programming added.

Bugfixes

Cortex M Trace: Fixed data trace correlation for exceptions.
ARM ETMV1 Trace: Improved trace decoder.
SR6P: Reduced connection time when HSM is enabled.
SR5E: Fixed regression for PLL calculation.
CoreSight Trace: Fixed possible crash during trace.
CoreSight Trace: Fixed tick calculation for port width greater 8Bit.
Cortex M debugging: Fixed password unlock for S32K3xx devices.
GTM v4 debugging: Fixed disassembler for C literal.
TC4 UCB configuration: UCB_CS_FLASH.DMU_GP_CSRM_DFPROCON corrected.
TC3 HSM: Better support for FLASH programming when SOTA mode is active.
Improved download speed of elf files with great number of small sections.
UDE® Sim SR6P6: Fix delay and error during start of trace.
UDE® Sim SR6P6: Fix implementation of instruction VLDR, literal version.
Code Coverage: Fix race between finished state and publishing reports in report history.
Code Coverage: Don't open window if core doesn't support Code Trace.
Tab stops in Tracedialog windows are not ordered correctly.
Mdf-Export cannot be imported in TA Toolsuite from Vector.
ArmETM: Improve ETMv1 trace decoder.
Incomplete number of assembler instructions for certain source lines.
Loading GNU RH850 ELF file results in 'Unknown file format'.
In certain cases stack window shows only addresses instead of function names.
TC3/DXCPL: wrong error message with erased PFLASH.
S32K3: password unlock does not work.
Occurring timeout cancels saving trace as tab.
RH850: step into does not work for fetrap instruction.
RH850: Reading Option Bytes after UDE® reset not possible.
RH850: incorrect error message when connecting to RH850/F1L.
RH850/U2B: Connect to ICUP via UAD2proV1/JTAG not possible.
XMC7000/ETMv4 - No trace being recorded after trigger on KIT_XMC72_EVK board.
Path management: second root path ignored.
Regression TC1793/PCP: Download fails.
Wrong Cortex-M callstack if R7 is used as stack pointer.
In certain cases no callstack info in case of HEX/ELF load.
Traveo II CYT3xx: Fixed tracing.
Executions Sequence Chart: show code at cursor time incorrect for big traces.

Changes from 2024.1 to 2025.0.2 (05.07.2024)

New Features

Make the Python interpreter optionally installable.
TC4x: XCP support added.
S32G: Added support for S25HS01G, S25FS256S, MX25U25645G, MX25UW51345G QSPI Flash.
RH850: Add IP polling.
Cortex Debugging: Support for i.MX RT1180 added.
Register database updates: STM32U5xx, S32Z.
Cortex Debugging: Support for i.MX RT1180 added.
PowerPc debugging: Support for C*Core CCFC3007, CCFC3008 added.
RH850: Support for RH850/U2C debug, flash, GTM, ICU added.
RH850: Support for RH850/P1x-C ICU added.
VC runtime package updated to 14.40.33810.
Default-Cfg file for R7F7017623x (RH850 F1KM-S2).
New application sample package 2024.

Bugfixes

TC2x/TC3x trace: Data Trace Chart does not show any data for miniMCDS traces.
TC3x miniMCDS trace: Data Trace Chart does not show any data for miniMCDS traces.
TC3x trace: Interpretation of data trace shows wrong bus master encoding.
CpuWin: Store numeric entry format when changed back to default, also.
CpuWin: Do not automatically change entry format, when number is entered in different format.
SFR window: fixed issues with enums in bitfields.
SFR window: fixed several scrolling issues.
SFR window: fixed writing to registers smaller then 32bit.
Fixed load of IAR ELF file with DWARF 4.
TC4x PPU: fixed memory filters.
RH850/U2B: regression ICUM option bytes fixed.
PowerPc trace: Fixed data range allocation.
Fixed selecting DAP clock for UAD2next.
Fixed CallStack display for RH850 with GHS compiler.
SFR window: Fixed regression loading content with legacy format.
TC4x: Remove SCR register from Host register database.
TC4x MCDS: Fixed decoding of multitick message.
TC2x/TC3x: Fixed password unlock for UAD3.
Callstack object model: fixed behavior for array-children.
Execution sequence: Fixed start time issue after refresh.
Callstack CortexV8 infinite recursion fixed.
Fixed UDE® slow download with many sections.
RH850 GTM deadlock during stepping.

Changes from 2024.0.6 to 2024.1 (03.05.2024)

New Features

ARTI trace adaption for MICROSAR from Vector.
RH850 Trace: Show watchpoints by their corresponding event in trace window.
RH850 Trace: Make timestamp synchronization period configurable.
SFR-Window: Write through also during periodical refresh.
Program time measurement for RH850 ICUP cores.
Cortex Debugging: Support for STM32U5Gx/STM32U5Fx added.
SR6 Debugging: Support for OTA X1 flash programming added.
Add maintenance expiration date to license manager dialog.
Show actual version of RLM-based license keys in license manager dialog.
Updated application note for SCR debug support for TC4Dx.
TC4 DXCPL support.
TC4x: add checks to UCB direct programming.
Add XCP chapter to UDE Manual.
Make breakpoint label editable.

Bugfixes

PXROS-HR: SimplyTrace® translation for Task Trace creates wrong analyze configuration for core1.
AURIX/HSM: download hang-up when HSM is not enabled.
Execution Sequence Chart: GTM TOM bitsignals have wrong labels.
Python console key binding wrong override for selecting word right from cursor.
FC7300: update access filters for PPB.
FC7300: Take care of exception mask in connect and reset.
RH850 Trace Configuration: show meaningful error message, if used events are not present.
License dialog: show actual version of RLM-based license keys.
Seldom crash during Save trace fixed.
Skip line records with line 0 (Hightec RUST 0.1.0).
XCP/SR6xx: FCCU error because XCP connect is too slow to disable watchdog.
TTA8: connect to low power target not possible after power on.
TC2 UCB_HSMCOTP programming: handling of set 2 confirmation corrected.
Cortex Debugging: Flash programming STM32U535/STM32U545 fixed.
SR6G7 PLL calculator regression fixed.
Breakpoint dialog is not accepting hexadecimal address as location.
TC4x/CDSP: Access to CDSP cores only available if all CDSP cores are enabled.
TC4x/CDSP: TC4x memory filter prevents reading non-mapped CDSP addresses.

Changes from 2024.0.5 to 2024.0.6 (28.03.2024)

New Features

Python-Add-In: Python 3.12.2 updated.
VC runtime package updated to 14.38.33135.
TC4Dx bootstrap loader support added.
AURIX: simplify access to COMDATA via automation interfaces.
Write several bit field changes at-once feature in peripheral window.
Documented API for SimplyTrace®.
RH850/U2x: Programming configuration/security/block protection area by a hex file.
FlagChip FC4x debugging and FLASH programming support.
RH850/U2B: Implement trigger for on-chip trace memory.
RH850/U2B: Implement support for global RAM capture device.
Breakpoint Window: Create Code Breakpoint.
Functions are displayed with name and parameter signature (GHS ARM C++).
Display class static variables with demangled class name (GHS ARM C++).
Make Cortex AHB PROT settings user configurable.
SR6P6: "External tool activation SW password" supported.
RH850/P1M-E: Debugging and FLASH programming support.
New S32Z/E B0 silicon revision supported.
SR6G7 register database update.
Peripheral window: MultiSelect Expand.
Cannot set breakpoints (DIAB TriCore compiler) .
Breakpoint is set to a wrong line (DIAB TriCore compiler).
AURIX: Warning about OCDSDIS without DBGIFLCK.
Support debugging of TC4D production devices.
Improve launcher update installation.
STM32H7xx Register database update.
AURIX/HSM: improve support for secure boot debugging.
RTOS Task Trace for MiniMCDS.

Bugfixes

TC3Ex LMU RAM range definition corrected..
TC2/3 UCB_DBG programming: warn about OCDSDIS without DBGIFLCK configuration.
Problem with periodic save workspace file during FLASH programming corrected.
TSim: Problem with reset-while-running corrected.
Core register window: Make entries read-only, if target is running.
Question to saving workspace after changing layout of peripheral window.
Question to saving workspace after adding register to peripheral window.
Core register window: During running show depend on target and refresh settings last value or '?' but not 0x0.
Peripheral window: Copy clicked instead previous selected cell.
UDEAPI: VBS compability restored for unsigned 32 bit results.
RTOS Window: Configure trace dialog does not reflect a previous configuration.
Peripheral window: Crash if export to invalid path is tried.
Breakpoint set to wrong address (GHS ARM compiler).
Wrong data for CoreSight/Nexus Aurora Trace with UAD2next using JTAG as debug interface.
RH850: Temporary halt after wakeup does not work with low JTAG frequencies.
FlagChip FMC7300: Improve multicore debug use case.
CodeCoverage and ESC are not working for TC4x trace.
XCP/SR6xx: Wrong CSW register values used for AXI/AHB accesses lead to FCCU error.
TC3Ex: LMU range definition is wrong.
ESC BTF export: there are events in the exported BTF-File.
ESC BTF export: ARTI 'wait for core'-transitions seem to be on wrong core.
Peripheral window: Remember Browse dialog options.
Peripheral window: Crash using DEL key during high CPU load.
STM32H7xx Dual Core: Slave core status wrong after application starting it.
UDE® Launcher: running instance handling in special cases not working as expected.
Cortex TargIntf enable automatic reconnect when changing OnHalt / OnStart.
UDE® Memtool: unwanted multicore connect.
STM32H745 improve only debug CM4 use case.
AURIX: suspend all cores on connect with break.

Changes from 2024.0.4 to 2024.0.5 (09.02.2024)

New Features

SimplyTrace® feature for TC4x MCDS.
FlagChip FMC7300: Debugging and FLASH programming.
Traveo II: eFuses support.
Traveo II: Support for Supervisory FLASH.
Call Graph Analysis: Export graph in machine readable format.
Support for more than 4 GB trace memory in Serial Trace Pod 100G.
AURIX TC2xx/TC3xx trace: Code and data comparators are now supported for GTM MCS.
Thinktec TTA8 debugging: HSM flash remapping support added.
S32Z: Support for W25Qxxx, IS25WPxxx SPI Flash added.
S32G: Added multiple locations for QSPI Flash.
SR6P3, SR6P6, SR6P7 Trace: Support for STLA / trace configuration based on HTQL.
AURIX Trace: GTM MCS data access based triggering added.
Frequently Asked Questions help file added.
RH850 support for Automotive Debug Adapter.
RH850: Provide possibility to drive FLMD0 during debug session.
RH850/U2B: Core Code and Data Trace.
Possibility to set DAP2_(USER0) and DAP3/DAPEN_(USER1) during debugging via object model (script).
UEC/GTM: Add LTQ config blocks "GTM: Signal MCS data access".
AppNote: Connect multiple targets to UAD3+ / use multiple UDE® instances.

Bugfixes

Cortex-R52: Call stack is sometimes not shown correct.
SR6 MC_ME.. register MER renamed to ME. Workaround removed.
Register Databases SR5E updated.
Register Databases S32M27 updated.
Thinktec TTA8 debugging: KeepRunning connect fixed.
Thinktec TTA8 debugging: LowPower debug improved.
Thinktec TTA8 debugging: Fixed programming secured flash.
Memtool: Fixed hanging Memtool UI when SFR refresh is enabled.
S32G debugging: Improved debugger connection behavior to S32G devices in QSPI boot modes.
AURIX HSM: Fixes program time measurement.
AURIX TC2xx: Can't disable PFLASH1 protection when PFLASH0 handling disabled.
SR6P7: Fixed GTM ARU trace.
SR6Px debugging: Improved connection behavior when HSM is deactivated.
SR6P: Improved TCM filters.
S32Z debugging: Improved connection behavior to protected devices.
SR6Px: Fixed life cycle programming in UTest FlashModExt.
CoreSight Trace: Fixed invalid P1 LHK decoding in special trace recordings.
AURIX Trace: GTM MCS code address based triggering fixed.
RH850/U2A: Connect not possible, when BIST enabled in OPBT.
RH850: Peripherals in self area not accessible.
RH850: wrong disassembly of dbtrap instruction.
RH850: Sometimes RH850 callstack is not displayed correctly (GHS compiler).
ARM: User defined label not visible (GHS compiler).
ARM: Wrong disassembly for long function.
SCR: Debugger assigns wrong address to variable in XRAM (HighTec compiler.
GTM: Slow periodic refresh of watch variables if GTM debugger is active.
Memory Window: Fix crash in heavy load situations.
Code Coverage: Fixed core selection regression in report dialog.
Code Coverage: Updated help for Create Report dialog.
Breakpoint edit dialog: Condition string was limited in length.
Breakpoint edit dialog: Configuring Loop Goal not possible.
Object model: Write access to array element via expression sub item not working.
Several SimplyTrace® improvements.
Several bug fixes in Peripheral Register window.
Updated AURIX SOTA AppNotes.

Changes from 2024.0.3 to 2024.0.4 (10.11.2023)

New Features

Python-Add-In: Python 3.10.13 updated.
Cortex M debugging: Support for Infineon T2G CYT3xx, CYT4xx and CYT6xx added.
Cortex M debugging: Support for Infineon XMC7xxx added.
Cortex M debugging: Support for S32K388 added.
Cortex M debugging: Support for STM32C011, STM32C031 added.
Cortex M debugging: Support for NXP KW45 Radio Flash update added.
Cortex M debugging: Support for eFuses added.
Thinktec TTA8 debugging: GTM trace support added.
Stellar: Support for SR6P3 completed.
TC4Dx: Support for PPU and CDSP cores added.
TC4x: MCDS trace feature added. Support for TC49x and TC4Dx dual MCDS trace units (on-chip RAM and SGBT).
CYT3xx/4xx/6xx: Added Coresight Trace support.
XCP/S32Z: Increase flashing speed.
Support SCR compiler from HighTec with OMF51 file format.
SimplyTrace® now also available for miniMCDS.
Float format is now also possible for data column in trace window.

Bugfixes

ARC: Sleep mode handling added.
ARC: Setting PC before disconnect not working.
XCP/S32Z: Connect to FETK-T5 not possible .
Function Profiling: Fixed use of wrong trace tick frequency for time calculation.
Execution Sequence Chart: Set lower limit on entry visibility.
Execution Sequence Chart: Fixed crash with XMC4500 CoreSight Trace.
Execution Sequence Chart: Export for chronVIEW from Inchron improved.
Code Coverage: Fix regression on result storage import and export.
Thinktec TTA8 debugging: JTAG unlock fixed.
Stellar debugging: Issue running from GTM data value breakpoint fixed.
Register Databases TTA8, S32K39x/37x updated.
S32G: Fixed regression on connect with invalid IVT and QSPI boot.
Stellar debugging: Flash driver manipulates system clock dividers fixed.
Saved trace text files contain no longer tabulator characters, explicit TAB separated files do it.
If persistent trace is unloaded the corresponding trace window is closed not the first one.
Browse dialog of SFR window is sometimes not visible in a three monitor setup.
Browse Dialog of SFR window is sometimes out of screen boundaries for 4K monitor.
Internal Python crashes when invalid alternate Python Home Path is set.
Python: __file__ variable not working in script.
Improve UAD2next Ethernet traffic: No TCP retransmission if later parts of big packet lost.
UAD2next: Error blink codes do not work.
Saved trace streams not available after UDE® crash.
SimplyTrace®: Enable interrupt detection for program trace - fails if filter is applied.
SR6Px Run from GTM data value breakpoint not working.
UDE® Automation: Inconsistent ByteOrder handling for UDEArray object.
MCDS: Very rare wrong decoding of Compact Function Trace for CALL.
GangProgrammer cannot load incomplete project files.
Code Coverage: Unable to select the directory for the report path and report pattern when disabling 'Create report for all Cores'.
Can't reconnect after UADx power-cycle.
SCR/XC800: 'Invoke SCR debugging' improved.
Random Crashes with PXROS AddIn.
Wrong core clock calculated for RH850/C1M-A1.
SFR-Window: Write only register now writeable.
SFR-Window: Size of scrollbar changes when scrolling.
UTF-8 text with Chinese characters is displayed wrong in program window.
Export SFR content to csv file is not working anymore.
Cannot load a certain A2L file containing 'ALIGNMENT_FLOAT16_IEEE' as alignment type string.
TC3xx UCB programming: UCB_HSM protection handling corrected.
TC4Dx UCB programming: UCB_RTC_USERCFG.LBISTEXE handling corrected.
TC4Dx UCB programming: UCB_CS_USERCFG handling corrected.
TC2xx UCB programming: UCB_OTP confirmation handling corrected.

Changes from 2024.0.2 to 2024.0.3 (25.08.2023)

New Features

AURIX trace: Predefined 'True (Always)' condition introduced in trace configuration libraries. Conditional action blocks can now be configured to behave like an Emit Actions block.
TC4Dx FLASH programming: UCB handling updated and extended.
TC3 FLASH programming: Improved handling of partly invalid UCBs.
VC runtime package updated to 14.36.32532.
TC4Dx debug support updated.
TC4Dx SCR debugging support added.
Thinktec TTA8 debugging: Initial support for V2 added.
Cortex M debugging: Support for TLE988x / TLE989x added.
Cortex M debugging: Support for NXP KW45 Cortex M33 added.
Stellar: Support for SSDP over CAN added.
Traveo II CYT2xx debugging: Added ETM and ITM trace with ETB and TPIU for Cortex M4.

Bugfixes

AURIX miniMCDS trace: Fixed a crash when using a target configuration or a workspace that requires features that are not covered by the current license.
TC4 STM suspend problem on halt by breakpoint fixed.
TC3 debugging: problem with 'sleep mode' detection fixed.
Execution Sequence Chart: Fixed broken "Show Code".
Stellar: Improved HSM NVM flash algorithm.
Cortex Debugging: Fixed program time measurement for S32K14x.
XCP/AURIX: Fixed DAP communication issue.
ETMv4 trace: Improve display of correlated data packages, based in transfer index.
Code Coverage: fix regression on clear data.
Watch window: Improve handling of very large arrays.
Can't set breakpoint on a function start (Compiler GHS TriCore) fixed.
If pointer target is changed to a valid address the watch window shows still '?' fixed.
Binary image load is different between HEX and ELF file for PSPR areas in PFLASH (Compiler GNU TriCore).
SR6Px Run from GTM data value breakpoint not working.

Changes from 2023.1 to 2024.0.2 (13.06.2023)

New Features

Cortex Debugging: Added support for STM32H745, STM32H755 dual core.
Cortex Debugging: Added support for YTM32B1ME Cortex M33.
Stellar: Support for SR6P7 completed.
Initial support for TC4Dx.
Possibility to set DAP2_(USER0) and DAP3/DAPEN_(USER1) during debugging via object model (script).
SimplyTrace® for OS Task Trace.
Periodically save workspace file.
Open program file: allow to select multiple elf/hex files at once.
TC4 FLASH programming: CS SOTA and UCB_CS_SWAP support added.
TC4 FLASH programming: UCB_BMHD protection handling updated.
Compatibility of the Eclipse plug-in with Eclipse 2023.
Support of new Data Consistency description (RB) format.
Initial HSPHY/SGBT implementation for UAD2next and TC49x.
XCP: Software Debugging over XCP with FETK-S2 and PowerPC.
Reprogram OPBT for RH850/C1x during connect via serial.
Improved graphical user interface for RTOS trace.
Stellar: Improved flash speed for XCP.

Bugfixes

Code Coverage: Date of trace start and stop is converted to wrong time zone.
Thinktec TTA8 debugging: Update register database.
S32Z: Fixed Infineon Semper X1 LPDDR4 flash support.
S32Z: Make option Mask assertion of FCCU Reset to a master only.
Cortex Debugging: STM32F7xx flash protection handling fixed.
Stellar: Fixed wrong behavior for cross wise swap.
Memtool/Traveo II: Flash driver address wrong.
Code Coverage - Date of trace start and stop is converted to wrong time zone.
Cannot set breakpoints except on function start - TI clang compiler.
Crash during load of corrupted ELF file from GNU TriCore C++ compiler fixed.
RH850: StopMode leads to connection loss.
Suppress __ghs_eofn_* labels to avoid wrong breakpoint descriptions (GHS compiler).
RH850/U2A and U2B: wrong checkbox description for S_OPBT7.DDRSTDIS.
Initialization of flash driver for RH850/F1K failed.
Product name check during connect with RH850/U2B6 R7F702556 failed.
S32Z: Fixed issue where slave cores are halted unexpectedly on break/connect.
SimplyTrace®: Several bug fixes.
SFR Window: Fixed deadlock while register refresh.
TC4x: Fixed GTM license issue.
RH850 LPD and JTAG clock inaccurate for low frequencies.
V850 Loop instruction disassembly is invalid.
Improve CRC calculation time for RH850/U2B Flash driver.
Register Databases CYT2, CYT3, CYT4, CYT6, SR6P6, TC4, TTA8 updated.
THA6: Fixed wrong program counter after Memtool execution.

Changes from 2023.0.7 to 2023.1 (28.04.2023)

New Features

Traveo II support added.
VC runtime package updated to 14.34.31938.
TC4 FLASH programming: FLASH protection/UCB_RTC_FLASH support added.

Bugfixes

Cortex A/R Debugging: Fixed not working big endian debug.
TC4x: Make SCR debugging more stable.
Thinktec TTA8 debugging: Prevent trace overflows von ETB trace.
TC4 FLASH programming: Broken UCB_RTC_USERCFG corrected.
Call stack support for RH850 GHS compiler.
Chipower THA6: Debug interface hangs when reading CAN peripheral memory.
Allow to change MCRC configuration in disconnected state.
ARC/THA6: Writing Safety Endinit (SE) protected register not possible with InitCmds.

Changes from 2023.0.6 to 2023.0.7 (06.04.2023)

New Features

SimplyTrace® feature introduced.
TC3 FLASH programming: UCB_ECPRIO support added.
SR6P6: Support for latest flash firmware added.
Code Coverage: Enhance performance of coverage tree.
Code Coverage: Integrate symbol browser into filter dialog.
Trace of NoC: NoC initiator and target can be added as separate column(s) to trace window.
Add C++ support for ARM compiler TI CLang.
TC4x: GTM debugging support.
RH850 debugging: RH850 C1x support added.
RH850 debugging: ICUM support of RH850/U2A and RH850/U2B devices added.
RH850 debugging: RH850/U2B GTM debugging support added.
Cortex Debugging: Support Renesas RA6xx Cortex M33 based derivatives added.
S32Z static JTAG unlock support added.
S32G3 eMMC support added.
S32G3 eFuses support added.
S32G static JTAG unlock support added.
Cortex Debugging: Support for NXP S32K396 added.
Cortex Debugging: Support for NXP S32K358 added.
Cortex Debugging: Support for NXP S32K312 and S32K311 added.
Cortex Debugging: Support for NXP S32M276 added.
Stellar: Support for SR6G7 added.
Thinktec TTA8 debugging: GTM debugging support added.
TC4 FLASH programming: RTC SOTA and UCB_RTC_SWAP support added.
TC4 FLASH programming: UCB_DBGCS support added.

Bugfixes

SR6X7 Trace (HTQL): Cross triggering of ETM events to STLA causes compilation error if more than one ETM event is issued.
SR6X7 Trace (HTQL): <client>_global_control needed for ETM events.
Register Databases S32K3xx updated.
UDE® Help fixed.
TC3 FLASH programming: UCB_BMHD content check function corrected.
Peripheral Register Window: Fixed several minor issues.
Core Register Window: Refresh after initial open restored.
XCP/AURIX: Accesses on single bytes/words are no longer done via read-modify-write but via correct width.
XCP/SR6x: Fixed connect when Core21 is in lockstep mode.
ARC: Fixed running after core was halted by configuration in trigger window.
Fixed trace issue on ETMv4 on first start trace after power on.
SR6P6: Fixes DCF parity calculation in UTest FlashModExt.
Trace Window: Fixed performance regression, when saving to tab file.
Code Coverage: Fixed initial load of storage file.
SR6X7 Trace: Bugfixes for HTQL related to events.
Error fixed when registering UDE.tlb with the UDE® register tool (register.exe).
ARC/Metaware: UDE® hangs during load of an ELF file from Metaware ARC compiler 14.0.6.
Watch/Locals: Font and/or font size should be selectable separately for normal and changed values.
SafeRTOS AddOn crashes if data on target is invalid.
Wrong location/value of local variable via automation interface fixed.
S32Z: improve HaltAfterReset connect behavior for different boot modes.

Changes from 2023.0.5 to 2023.0.6 (20.01.2023)

New Features

Thinktec TTA8 debugging: Add OnChip trace support.
SR6X7 Debugging: Support of single ended programming.
SR6X7 Debugging: Support of OTA NVM features (Extend, Swap, Refresh).
S32Z: Added smart debugger access filters for SPI, Netc, DDR.
S32G: OnChip trace for S32G3xx added.
Cortex Debugging: Support for NXP S32M244 added.
XCP Debugging: Preliminary support for S32Z270 debugging.
SR6X7 Trace: Initial support for STLA / trace configuration based on HTQL.
Support for TC23x-16F variants with 1MB PFLASH added.
Context depend navigation from ORTI view to other windows added.
Execution Sequence Chart: Provide snap to data point function for markers.
Code Coverage: HTML Reports can also opened in an external browser.
ICUM support of RH850/E2M and RH850/E2H devices.
AURIX: ABM/BMI header handling improved.
Execution Sequence Chart: Improve BTF export for better compatibility to third party tools.
TC4x: Simplify start configuration with Core 0/Core CS configurations and shared ELF file.
TC4x: Initial GTM debugging.
S32S, S32G: Initial AURORA support.
Preliminary support for TC4Dx.

Bugfixes

S32Z: Data value breakpoint for Cortex M fixed.
S32Z: Fixed issue of hanging trace configuration for HTM.
Register Databases Cortex R52, SR6P6, SR6P7G7, SR6P7, TTA8 updated.
Fixed issue where UAD2x gets not recognized via USB in Citrix virtual environment.
Memtool: Fixed issue with CRC is not executed albeit driver reports CRC32 capability.
ARC/THA6: Fixed DFLASH programming.
XCP Debugging: Using maximum CTO length for XCP commands if available.
XCP Debugging/AURIX: Fixed issue where time-consuming LLTs were used but not required.
Long filter strings in symbol explorer will no longer cut.
New SFR Window: Tooltips of Bitfields are getting cut at the end.
Wrong display of global variables fixed (GNU ARC).
Trace Window: Tick format not persistent.
New SFR-Window: Empty window not properly saved.
New SFR Window: Removing a register does not remove the corresponding target access.
Automation: Don't show error message boxes.
RH850: fixed disassemble error of 'Bcond' instruction.

Changes from 2023.0.4 to 2023.0.5 (16.12.2022)

New Features

RH850 debugging: Added dialog for peripheral specific break on halt configuration.

Bugfixes

RH850 debugging: several smaller bugfixes.

Changes from 2023.0.3 to 2023.0.4 (18.11.2022)

New Features

TC4x trace: Initial on-chip trace support.
TC4x trace: Initial version of graphical trace configuration (UEC).
Memtool: New programming option 'Fill all sectors with user defined byte' added.
Trace: Add manual synchronization of Call Graph Analysis and Trace Window by timestamp.
Execution Sequence: Improve user interface and user controls.
Cortex Debugging: Setting AB1_DIS pin implemented.
Cortex Debugging: Added support for STM32F413xH, STM32F413xG, STM32F423xH.
S32Z Cortex M33: Added support for initialization commands with secure mode.
S32Z: GTM v4 trace support added.
S32G: Support for S32G3xx added.
ARC: Initial support for Chipower THA6 added.
RH850/E2M and Rh850/E2H basic debugging support.
S32Z: Initial AURORA support.
TI Sitara: Now FLASH driver also at core R5_0_0 (Cortex R5).
Add *.abs as default file type for program files.
Allow to launch UDE® with hidden main window.
Multicore debugging for TTA8 chip from Thinktec.

Bugfixes

Arm Trace: Fixed not working ETMv4 trigger.
TC4 debugging: STM suspend after connect corrected.
TC4 debugging: Time measurement in multicore-config corrected.
TC4 debugging: Elf file handling for CDSP cores corrected.
UAD2+: Fixed accessibility issues via ethernet.
XMC4800 FLASH programming: Fixed display bug for protected sectors.
UAD2next: Fixed UDE® hangup using Time Trace Chart.
SR6: Improve setting breakpoints for inactive cores.
Register Databases SR6P7G7, SR6P6, S32E27 updated.

Changes from 2023.0.2 to 2023.0.3 (30.09.2022)

New Features

S32G: Initial OnChip Coresight trace support added.
S32Z: GTM v4 debug support added.
SR5E: MultiCore support for StellarE.
SR5E: Coresight Trace support for StellarE.
Cortex R52 Debugging: Add user defined TCM mapping support.
TC3x + HSM: Improve emergency connect options in case of broken boot configuration.
XCP/AURIX: Allow setting AB1DIS pin on connect.
Basic debugging and FLASH programming for TTA8 chip from Thinktec.
Automation: Add MultiCoreLoader.Get/SetFileActive functions.
Support of RH850 E1L and E1M-S2 series.
RH850/U2B basic debugging support.
Execution Sequence Chart: Call-depth entry should not be sorted.
Execution Sequence Chart: Change Sensitivity of Zoom and vertical Scrolling.
TC4x/CDSP: Initial debug support.

Bugfixes

UDE® Memtool: load bin file function corrected.
Data Correlation loses correlation alignment in case of missing NDSM and multiple UDSM at trace begin.
SR6P6: Fixed UDE® HSM PFlash description.
Cortex Debugging: Fixed STM32F7 regression.
Fixed deadlock during start of user application.
GTM Debugging: Fixed issue during cleanup of breakpoints on stepping resulting in unexpected target halts.
Several bugfixes in new SFR window.
TC4x: Standalone UDE® Memtool doesn't handle CS FLASH modules.
Automation: Write access to structure element via Item property fails.
RH850: Inline Assembler doesn't work for opcode with indirect access/branch.
RH850: Debug and system registers could not be written via init commands.
Variable not readable via COM-API if symbol file with ID2 and Variable not already expanded in Watch Window.
Multicore UDE® läuft nicht auf Jenkins Server.
XCP/SR6P7G7: Fixed crash when opening workspace.
ARC SmaRT Trace: Fixed tracing loops.
Register Databases RZ/N2 R9A07G084, TTA8, SR6P6, Stellar, S32E27 updated.

Changes from 2023.0.1 to 2023.0.2 (29.07.2022)

New Features

TC29x trace: Compact Function Trace (CFT) for miniMCDS now available with Compact library.
Support for S32E278 introduced.
SR5E: Initial support for StellarE.
Phyton: Folder of last loaded script now saved in workspace.
S32Z: SPI flash driver build variant for SMU SRAM3.
ARC: SmaRT trace support introduced.
UDE® Memtool: provide 'remove file sections' function.
UDE® Memtool: add 'automatic start VerifyAll' option.
Context menu entry to configure program trace out of program window.
Execution Sequence Chart: Add Control and Data interfaces for Object Model.
Call Graph Analysis: Introduce "Go To" to the same node between graph and function view.
S32E27 OctalFlash programming.
TC4x: SCR debugging support.
S32E27 eMMC programming.
TC4x: initial debugging in virtualization mode.

Bugfixes

TC29x trace: Fixed miniMCDS trace decoder for compact function trace.
Cortex: Fixed access to AArch32 floating point special registers.
S32Z2: Added new build variant for SMU flash SPI driver.
PowerPc debugging: UEC not working for SPC572 fixed.
PowerPc debugging: Fixed invalidate cache issue debugging NMI exception handler.
Eclipse plug-in: watch window periodic refresh not working fixed.
'Save as' for correlated ETMv4 trace does not work fixed.
IP display does not work correctly and UDE® hangs on close workspace if a SentinelOne client is active fixed.
Crash after error message "A new guard page for the stack cannot be created" fixed.
Enum variables from symbol files where ID > 1 cannot set symbolically via automation functions if the enum values not already in database.
ARMv8 AArch32 Access to floating point special registers not possible fixed.
TC4x/PPU: PPU should not be started initially by multi-core run control.
Macro: Invalid hotkey assignment to macro function.
Call Graph Analysis: Fix initialization of analysis for XMC4500.
Execution Sequence Chart: Fixed handling of function names with special characters.
Profiling Trace: Catch exception during trace analysis.
Data Correlation: Fixed creating of invalid input for correlation analysis.
TC3+HSM: Connect problem with broken boot config fixed.
UAD2next: Fixed accessibility issues via ethernet.

Changes from 2022.1 to 2023.0.1 (10.06.2022)

New Features

Changing build technology: VS2022, Win10 SDK, VC runtime package 14.32.31326.
Global UDE® Time: Initial implementation of Global Time Service.
Global UDE® Time: Make Call Graph Analysis a time series provider.
Call Graph Analysis: Implement feature "Show in {Graph,Functions}".
Automation: High level trace configuration with first use case 'ORTI TASK Trace'.
Support for TI Sitara (AM64x, AM243x).
External OSPI programming support for TI Sitara.
Support of XCP access devices from Vector (VX1060 + VX1543A) for AURIX targets.
S32G: Add support for SPI flash Micron MT35XL/U[256,512,01G,02G].
Default memory access filter list for TC4x support.
Automation: MultiCoreLoader.RemoveAllFiles also remove loaded sections from Memtool.
Filter in Message window now also usable for export.
More descriptive error message for unsupported SPI flash.
ARM ETMv4: Introduce trace package 'data access' for accesses with unknown r/w type.
TriCore/AURIX: Update TSIM to version 1.18.136.
Python-Add-In: Python 3.10.4+ updated.

Bugfixes

Call Graph Analysis: Remove values for static call graph exclusive counter.
Crash on Close Workspace when Python Script Console was used.
Execution Sequence Chart: Help updated.
Automation: Sometimes hang-up on automated multifile/multicore download if driven by ECU test.
In multi master configurations e.g. Core + HSM sometimes Memtool dialog pops up too early.
Unwanted errors/warnings from TC4x disassembler avoided.
ARC: Add cache handling to UAD firmware e.g. for software breakpoints.
ARC: Reading and writing ARC EV vector and predicate registers.
TC4x/PPU: Improve safety (debuggable vs non-debuggable) level handling.
SR6P6: Implement filter for accessing DMA VMID registers.
S32G: Debug Cortex M7 with Cache enabled is not possible.
S32Z2: Wrong Core and System registers for Cx M33 cores fixed.
S32Z: Cortex M33 detection state change from inactive to running not working.
UAD2next Connect C16x ASC ROM monitor connect unstable.
S32E/Z: S32E core halt after wakeup.
S32Z: Core00 unexpected halt after boot from SMU.
S32Z: Connect SMU fails when QSPI boot is enabled.
UDE® stucks with a certain AURIX HSM ELF file (Tasking ARM).
UDE® crashes after loading a certain ELF file (STM Cube IDE 1.7.0) or after reconnect if this file is loaded.
With a certain file ARM/Thumb mode display is wrong (GHS ARM).
Execution Sequence Chart: HSM Trace displayed as addresses only.
Execution Sequence Chart: Help and Manual updated.
Some inline assembler defined functions not displayed (GHS ARM).
Execution Sequence Chart: For HSM only trace wrong core name is displayed.
Execution Sequence Chart: Crash when using Move to Next/Previous in an empty chart.
Execution Sequence Chart: Invalid start at tick 0.
Python input function corrected for SHIFT+<key> inputs.
UAD2next: Fixed accessibility issues via ethernet.