Multicore Debug and Trace Support for NXP S32G3 Vehicle Network Processors
March 14, 2023
With the latest version UDE 2023 of the Universal Debug Engine, PLS Programmierbare Logik & Systeme also extends their multicore debug and trace support to the S32G3, the newest series of NXP® Semiconductors’ S32G family of Vehicle Network Processors. PLS will show a tool demo at embedded world 2023 in Hall 4, Booth 4-310.
The NXP S32G3 extends the S32G family which is part of NXP’s S32 Automotive Platform. Designed for central vehicle compute applications in zonal-based, software-defined vehicles, the S32G3 provides a higher-performance upgrade for gateways, domain control and safety processing. To meet the high demands of autonomous driving and next generation ADAS, the S32G3 combines highest ASIL D and hardware safety with high-performance real-time and application processing.
For maximum scalability, the S32G3 comes with the same pinout as the other members of the S32G family. Up to eight Arm® Cortex®-A53 cores organized in two clusters of four cores with optional cluster lockstep, provide the computing power for application and services. Dedicated for real-time applications additionally up to four Arm® Cortex-M7 dual-core lockstep (DCLS) complexes are integrated in the devices. A Hardware Security Engine (HSE) for secure booting and accelerated security services contributes all the necessary functions to meet the high safety requirements of current and future vehicle applications.
To make the most of the performance of the S32G3, PLS' UDE 2023 offers system developers comprehensive support for multicore debugging and tracing. Among other things, the latest version of the Universal Debug Engine features a simple and intuitive usage that enables extremely efficient debugging and runtime analysis of applications for the new NXP devices. The main Cortex-A53 processor cores and the Cortex-M7 cores are all visible and can be controlled within one common debugger user interface. There is no need to open separate debugger instances for the different core architectures.
For real multicore debugging, the multicore run-control management of UDE provides flexible controllable synchronization of cores of the S32G3 for run-mode debugging. Breakpoints or single steps work on all cores, on core groups, or on a single core, depending on the requirements of the particular debug task. All cores in such a run-control group can be started and stopped almost synchronously. This helps to keep a consistent state of the respective application during debugging. Multicore breakpoints also simplify the debugging of complex applications, especially in shared code. A multicore breakpoint is effective regardless of which core is currently executing the specific code.
For in-depth system-level analysis and non-invasive debugging of multi-core applications, UDE provides extensive functions based on recorded trace information Arm® CoreSight® trace system. This enables investigation of typical issues of parallel execution or timing problems. Based on trace, UDE offers a lot of analysis functions such as profiling, call graph analysis and also code coverage for proofing the quality of software tests. Besides the trace functions for the Cortex-A53 cores as well as the Cortex-M7 cores, UDE also provides support for tracing the transactions via the Network-on-Chip (NoC) used for the communication between the cores and the other components of the S32G3.
To store the captured trace data, either the UAD2next or the UAD3+ from the PLS’ Universal Access Device family can be used. The UAD2next features 512 MB of trace memory and the UAD3+ up to 4 GB. The fast download of the trace data from the chip towards the UDE is done via the High Speed Serial Trace Port (HSSTP) of the S32G3 up to 5 Gbit/s per lane.
Simple and safe programming of OctalSPI flash for the S32G3 is enabled by the MemTool add-on, which is an integral part of the UDE. eMMC as well as OCOTP (On Chip One-Time Programming) are also supported.