TriCore™ AURIX™ TC32, TC33, TC34, TC35, TC36, TC37, TC39 Microcontrollers from Infineon

The multi-core SoCs of the AURIX™ TC32x, TC33x, TC35x, TC36x, TC37x, TC38x, TC39x were specifically designed for electric and/or autonomous vehicles. Among other features, they offer a 300% increase in processing power compared to current high-end automotive microcontrollers. The MCUs included in the scalable AURIX™ TC3xx family can be equipped with up to 16 Mbytes of embedded Flash memory, more than 6 Mbytes of RAM and up to six 32-bit TriCore™ processor cores that operate independently. An additional lockstep core is included in four of the six TriCore cores supporting clock frequencies up to 300MHz, resulting in up to 2,400 DMIPS of processing performance for systems providing the highest safety assurance level (ASIL-D). Additional features of the TC3xx family include a radar processing unit with up to two Signal-Processing Units and a Hardware Security Module (HSM) encompassing asymmetric cryptography mechanisms meeting the requirements of EVITA ‘high’. For use as host controllers in gateway and telematics applications, the devices also support a Gigabit Ethernet interface, up to 12 CAN FD channels according to ISO 11898-1 and a maximum of 24 LIN channels.

The existing Infineon TriCore AUDO™ architecture is well-known for a sophisticated On-Chip Debug System (OCDS). This was optimized further for the Aurix family and adapted to the requirements of multicore debugging. With the new Aurix devices, the following interfaces are provided for debug, test and calibration tools: JTAG with up to 40 MHz serial clock, 2-pin and 3-pin Device Access Ports (DAP) as well as a 3-pin DAP2 with up to 160 MHz serial clock. The block transfer rate of the DAP2 could be increased almost three-fold to 30 MByte/s by means of an optimized protocol. The development with associated tool manufacturers such as PLS was supported by suitable hardware tools such as for example the Universal Access Devices (UAD2/UAD3+) family.

• 32-bit architecture
• 6 TriCore cores
• 4 GByte unified data, program, and input/output address space
• 16/32 Bit instructions for reduced code size
• Low interrupt latency
• Fast automatic context switching
• Multiply-accumulate unit
• Saturating integer arithmetic
• Bit handling
• Packed data operations
• Zero-overhead loop
• Flexible power management
• Byte and bit addressing
• Little-endian byte ordering
• Support for big- and little-endian byte ordering at bus interface
• Precise exceptions
• Flexible interrupt prioritization scheme