ST10™ ST10F276, ST10F269, ST10F296 Microcontrollers from STMicroelectronics

Microcontroller Debugger solutions for ST10™ ST10F276, ST10F269, ST10F296 from STMicroelectronics

The architecture of the ST10F269 combines the advantages of both RISC and CISC processors in a very well-balanced way. The sum of the features that are combined result in a high-performance microcontroller, which is the right choice not only for today's applications but also for future engineering challenges. The ST10F269 not only integrates a powerful CPU core and a set of peripheral units into one chip but also connects the units in a very efficient way. One of the four buses used concurrently on the ST10F269 is the XBUS, an internal representation of the external bus interface. This bus provides a standardized method of integrating application-specific peripherals to produce derivatives of the standard ST10F269.

  • 50 ns minimum instruction cycle time, with most instructions executed in 1 cycle
  • 16 x 16-bit multiplication, 40-bit Accumulator
  • Multiple high-bandwidth internal data buses
  • Register based design with multiple variable register banks
  • Single cycle context switching support
  • 16 MBytes linear address space for code and data (von Neumann architecture)
  • System stack cache support with automatic stack overflow/underflow detection
  • Bit, byte, and word data types
  • Flexible and efficient addressing modes for high code density
  • Enhanced boolean bit manipulation with direct addressability of 6 kbits for peripheral control and user defined flags
  • Hardware traps to identify exception conditions during runtime
  • HLL support for semaphore operations and efficient data access
  • 2 kByte internal RAM for variables, register banks, system stack and code
  • up to 10 kByte on-chip high-speed XRAM for variables, user stack and code (not on all derivatives)
  • up to 256 kByte on-chip Program FLASH Memory (not for romless devices)
  • Multiplexed or demultiplexed bus configurations
  • Segmentation capability and chip select signal generation
  • 8-bit or 16-bit data bus
  • Bus cycle characteristics selectable for five programmable address areas
  • 56 interrupt nodes with separate interrupt vectors
  • 240/400 ns typical/maximum interrupt latency in case of internal program execution
  • Fast external interrupts
  • Interrupt driven single cycle data transfer
  • Transfer count option (standard CPU interrupt after a programmable number of PEC transfers)
  • Eliminates overhead of saving and restoring system state for interrupt requests
  • 16-channel 10-bit A/D Converter with programmable conversion time (4.85 us minimum), auto scan modes, channel injection mode
  • Two 16-channel Capture/Compare Units with 2 independent time bases each, very flexible PWM unit/event recording unit with different operating modes, includes four 16-bit Timers/counters, maximum resolution fCPU /8
  • 4-channel PWM Unit
  • Two Multifunctional General Purpose Timer Units GPT1: three 16-bit timers/ counters, maximum resolution fCPU /8 GPT2: two 16-bit timers/counters, maximum resolution fCPU /4
  • Asynchronous/Synchronous Serial Channels (USART) with baud rate generator, parity, framing, and overrun error detection
  • High Speed Synchronous Serial Channel programmable data length and shift direction
  • Two On-Chip CAN Bus Module, Rev. 2.0B active (30 or 2x15 Message Objects)
  • Watchdog Timer with programmable time intervals
  • ASC Bootstrap loader for flexible system initialization
  • CAN Bootstrap loader for flexible system initialization

Supported Microcontroller's

  • ST10R163
  • ST10F163
  • ST10R165
  • ST10R167
  • ST10F167
  • ST10F168
  • ST10F169
  • ST10R172
  • ST10F251
  • ST10F252
  • ST10F269
  • ST10R271
  • ST10R272
  • ST10R273
  • ST10F275
  • ST10F276
  • ST10F280
  • ST10F282
  • ST10F296


UDE - Universal Debug Engine - Debugger and Emulator for ST10

UDE - Universal Debug Engine - is a flexible debug platform for STMicroelectronics ST10.

Ordering code

UDE-LIC-C166/ST10 / <Selected Access Device>