TriCore™ AURIX™ TC39, TC38, TC37, TC36, TC35, TC33 Microcontrollers from Infineon 2nd Generation
Microcontroller Debugger solutions for TriCore™ AURIX™ 2nd Generation TC39, TC38, TC37, TC35 from Infineon
Infineon AURIX™ is an enormous increase in performance. With its high-performing hexa-core architecture and its advanced features Infineon AURIX™ (AUtomotive Realtime Integrated neXt generation architecture) second generation, an extremely high-performance microcontroller (MCU) platform meets the requirements for powertrain and safety applications of the automotive industry.
The multi-core SoCs of the second AURIX™ TC39x generation were specifically designed for electric and/or autonomous vehicles. Among other features, they offer a 300% increase in processing power compared to current high-end automotive microcontrollers. The MCUs included in the scalable AURIX™ TC3xx family can be equipped with up to 16 Mbytes of embedded Flash memory, more than 6 Mbytes of RAM and up to six 32-bit TriCore™ processor cores that operate independently. An additional lockstep core is included in four of the six TriCore cores supporting clock frequencies up to 300MHz, resulting in up to 2,400 DMIPS of processing performance for systems providing the highest safety assurance level (ASIL-D). Additional features of the TC3xx family include a radar processing unit with up to two Signal-Processing Units and a Hardware Security Module (HSM) encompassing asymmetric cryptography mechanisms meeting the requirements of EVITA ‘high’. For use as host controllers in gateway and telematics applications, the devices also support a Gigabit Ethernet interface, up to 12 CAN FD channels according to ISO 11898-1 and a maximum of 24 LIN channels.
The existing Infineon TriCore AUDO™ architecture is well-known for a sophisticated On-Chip Debug System (OCDS). This was optimized further for the Aurix family and adapted to the requirements of multicore debugging. With the new Aurix devices, the following interfaces are provided for debug, test and calibration tools: JTAG with up to 40 MHz serial clock, 2-pin and 3-pin Device Access Ports (DAP) as well as a 3-pin DAP2 with up to 160 MHz serial clock. The block transfer rate of the DAP2 could be increased almost three-fold to 30 MByte/s by means of an optimized protocol. The development with associated tool manufacturers such as PLS was supported by suitable hardware tools such as for example the Universal Access Devices (UAD2/UAD3+) family.
- 32-bit architecture
- 6 TriCore cores
- 4 GByte unified data, program, and input/output address space
- 16/32 Bit instructions for reduced code size
- Low interrupt latency
- Fast automatic context switching
- Multiply-accumulate unit
- Saturating integer arithmetic
- Bit handling
- Packed data operations
- Zero-overhead loop
- Flexible power management
- Byte and bit addressing
- Little-endian byte ordering
- Support for big- and little-endian byte ordering at bus interface
- Precise exceptions
- Flexible interrupt prioritization scheme
Supported TriCore™ Cores
- TriCore™ 1.6.2P
- TC32 TC322 TC323 TC324 TC33 TC332 TC334 TC336 TC337 TC35 TC356 TC357 TC36 TC37
- TC370 TC375 TC377 TC38 TC380 TC387 TC389 TC39 TC397 TC399
- TC33xED TC35xED TC37xED TC39xED
UDE - Universal Debug Engine with MCDS, Aurora Gigabit Trace, OCDS, DAP, DAP2 Support - Debugger and Emulator for Infineon Multicore TriCore AURIX 2G (MCA)
UDE - Universal Debug Engine - is a flexible debug and emulator platform for multi-core debugging of Infineon's TriCore AURIX 2nd Generation (MCA).
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