PLS' new universal multicore workbench simplifies multicore control and debugging at system level

Lauta (Germany) – January 10, 2012 – PLS Programmierbare Logik & Systeme presents its Universal Debug Engine (UDE) 3.2 for the first time at embedded world 2012, Nuremberg in Hall 4, Booth 4-310 from February 28 to March 1, 2012. The UDE 3.2 features new functions for a particularly efficient multicore control, unique visualization capabilities at system level and the dedicated support for a wide range of the latest 32-bit SoCs from different manufacturers.

The UDE 3.2, which is enhanced to a universal multicore workbench for the Development Device of Infineon's new TriCore multicore architecture as well as devices from the STMicroelectronics/Freescale Joint Development Program (JDP), includes a multicore program loader that controls loading of the application to multiple cores as well as a multicore run control manager for synchronous runtime control. Therefore, the data recorded by the on-chip trace like Infineon's Multi-Core Debug Solution (MCDS) or externally (Nexus or CoreSight) can be visualized and used for analysis functions at the system level such as code coverage or profiling. The graphical code coverage analysis enables simple recognition of non-executed code at function, source line or machine code level. Profiling functions help with performance optimization of applications.

Other microcontrollers (MCUs) supported by the UDE 3.2 include Infineon's new AUDO MAX TC1791, TC1793 and TC1798 devices, which are based on the TriCore version 1.6. The emulation devices of this high-end MCU family, which are specifically designed for troubleshooting and calibration, offer the user significantly advanced diagnostic capabilities in combination with the further improved Universal Emulation Configurator (UEC) of the UDE.

The latest version of the UDE also promises dedicated support for the Power Architecture based SPC56x devices from STMicroelectronics and the Qorivva MPC56xx family from Freescale. With the UDE 3.2, for example, both cores of dual e200 core derivatives can be debugged within one user interface - both in the safety-relevant lock step (LS) mode and the decoupled parallel (DP) mode.

In addition, the support for various Cortex M derivatives such as the Cortex-M3 based STM32F2 family from STMicroelectronics, the LPC178x family from NXP and the Cortex-M4 based Kinetis series from Freescale was expanded. Furthermore, all CoreSight technologies such as Serial Wire Debug (SWD), Serial Wire Viewer (SWV), Instrumentation Trace Macrocell (ITM) and Enhanced Trace Macrocell (ETM) can be fully and effectively used by the debugger.

Moreover, Hilscher's netX 50/100/500 network controllers and the rcX real-time operating system, which is specifically optimized for the netX controllers, are also supported for the first time by the UDE. The rcX add-on of the UDE 3.2 enables the user a full presentation of the operating system objects. Individual views show the application instances of tasks, queues, mutexes, semaphores, timers, interrupts and UARTS with their characteristics and current status, whereby the active tasks and the stack utilization of all tasks are each recognizable at a glance.

The UDE 3.2 is available for all 32-bit and 64-bit versions from Windows XP to Windows 7 and can be integrated at no extra cost in Eclipse environments. Access to the target takes place via the supplementary Universal Access Devices UAD2 or UAD3+ from PLS, whereby the UAD3+ enables the user multi-target support with debug clock rates of up to 100 MHz, up to 4 GByte trace memory (Nexus, CoreSight ETM) and recording of trace signals up to 500 MHz.