On-chip Trace and Profiling - MCDS, OCDS L2, ETM, ETB, Nexus, Triggered Transfers
In depth real-time debugging requires close interaction with the processor. Tracing shall provide a chronological picture of a system's inner
workings - before or after a critical event - mainly to help analyzing
a faulty program.
UDE Profiling Support
The knowledge of CPU load distribution of the running target application is a basic requirement to optimize their real-time behavior. The analyzing functions support the viewing, profiling and detecting of the recorded data and is realized by different views of Universal Debug Engine to display the results of recorded IP trace and data trace from different sources: "IP - Snooping" trace of instruction pointer of TriCore, XC166, XC2000 and Cortex-M3 CPU periodically with minimum poll period of 1 millisecond. Nexus, CoreSight, ETM, ETB, MCDS and OCDS L2 code trace are supported.Trace Visualization and Analyzing
The trace data of the instruction pointer will be collected according to their occurrence in functions of the application. If the address value cannot be assigned to any known function, it will be assigned to known code sections of the program (depending on debug information). The evaluation counts the hits of appropriate ranges and calculates the execution time of the ranges via the execution time of the trace samples.The results are available as chart diagram and as numeric result table. The results can be saved in a free selectable XML base data sink for later processing using the UDE Profiling page. This data sink can be processed in a normal MS Excel 2003 environment or can be processed by Windows Script languages and MS XML parser function (which are installed by UDE). All functions to access to the generated profiling data are also available via the UDE object model to allow creation of internal and external scripts for automatic post-processing.
Multi-Core Debug Solution MCDS Instruction Trace
The Multi Core Debug Solution (MCDS) integrated on the Emulation
Extension Chip (EEC) of Infineons TC1796ED and TC1797ED is a powerful
trace and event generation module. This new full-featured emulator
onsilicon opens a new age of debugging capabilities.It allows to
observe and control the running system in a very purposeful way.
Elaborated filter mechanisms and a high visibility to the system
internals (cores and busses) are the key features of MCDS. To make use
of them the MCDS has to be configured for each trace task using the
Universal Emulation Configurator (UEC).
Universal Emulation Configurator (UEC) for TriCore Emulation Device
The Universal Emulation Configurator (UEC) is the hardware-independent tool
to describe measuring tasks for on-chip emulators and is comparable
with development environments for the hardware draft. With its
assistance development engineers can also create configuration data for
an on- chip emulator without large expenditure of time and this
independently of the respective target hardware.
With the
"Universal Emulation Configurator" the developer gets a top-notch
configuration tool just right for demanding measuring tasks with
on-chip emulators.
Major benefits of using the UEC are:
- Functional description on basis of a state machine
- Being independent from the respective target and emulator hardware
- Fast and simple definition of complex measuring tasks
MCDS is supported by the TriCore family, including TC1766ED, TC1796ED, TC1767ED, TC1797ED derivatives.
Universal Emulation Configurator 2 (UEC2) for XC2000 Emulation Device
The
so-called emulation device XC2000ED with integrated on chip emulator is
available for development and test purposes. Up to now only the
Universal Emulation Configurator UEC2 from PLS offers a complete
support of this high-performance debug hardware. This is especially
true for the integrated performance counter of the XC2000ED. With this
unit, important data - such as instruction counter, interrupt
acknowledges, stall and idle cycles and many more - can be recorded and
analyzed for application optimization.MCDS is supported by the XC2000ED family, including XC2080ED and XC2090ED.
XC2000/XE166 Emulation Devices
The XC2000ED Emulator offer the usage of MCDS-driven XC2000EDs in the customer's hardware on a flexible way.On Chip Debug Support OCDS L2 Instruction Trace for TriCore
The OCDS L2 (On-chip Debug Support Level 2) unit of the TriCore derivatives
supports the recording of a running program's trace. In combination
with the JTAG OCDS L1 unit a comfortable watching of the program flows
of the core, the PCP/PCP2 processor and the DMA processor in real-time
are possible. UDE supports the OCDS unit by the Universal Access Device
- Trace Board option. 60 Pin OCDS L2 High-speed Connector Pod
- Proposed by Infineon to support connection to OCDS L2 port of TriCore 1.3 systems (TC11xx, TC17xx, TC19xx and future derivatives)
- Connector system based on SAMTEC 60 pin highspeed connector QSH-030-01-F-D-A
- Prepared to use for systems up to 180 MHz system clock
- Supports 2,5V to 3,6V I/O ring voltage
MCDS and OCDS L2 Trace Feature Comparison
TriCore Microcontrollers
The following table gives an overview about the OCDS L2 and MCDS trace features of the Infineon TriCore microcontrollers.| Feature list | MCDS | MCDS | OCDS L2 |
|---|---|---|---|
| TriCore Derivatives | TC1767ED, TC1797ED | TC1796ED, TC1766ED | TC1130, TC1161, TC1766, TC1796, .. |
| TriCore Instruction Pointer Trace |  | | |
| DMA Trace | | | |
| PCP Instruction Pointer Trace | | | |
| PCP Channel (Priority) Trace | | | |
| Data Trace, Watch point Trace, Bus Trace | | | |
| TriCore-PCP mixed Instruction Pointer Trace | | | |
| Number of Ranges to be traced simultaneously | 6 ranges for TC, 4 ranges for PCP | 6 ranges for TC, 4 ranges for PCP | 1 range |
| OCDSL1 Trigger Condition | | | |
| Sequential Trigger Condition | | | |
| Reference-Clock (USB-Clock) based Time Stamps | (emulation clock or FlexRay clock) | (emulation clock or USB clock) | |
| Time based Trigger Condition | | | |
| Tick based Time Stamps | | | |
| Single shot Time Stamps for Time measurement | | | |
| Stopping TriCore and/or PCP on Trigger Condition | | | manual configuration |
| Emitting Signal on external Break pin on Trigger | | manual configuration | |
| Performance counters | | ||
| Connector | 16-pin standard JTAG Connector | 16-pin standard JTAG Connector | 60-pin OCDS L2 Connector with Trace pod |
| UDE-Tool Ordering Code | UDE-TC/UAD2 and UDE-TC UEC | UDE-TC/UAD2 and UDE-TC UEC | UDE-TC/UAD2+ and UDE-TC L2 |
XC2000 Microcontrollers
The following table gives an overview about the MCDS trace features of the Infineon XC2000 Emulation Device microcontrollers.| Feature list | MCDS |
|---|---|
| XC2000ED Derivatives | XC2080ED, XC2090ED |
| Instruction Pointer Trace | |
| Data Trace, Watch point Trace | |
| Number of instruction pointer ranges to be traced simultaneously | 4 ranges |
| OCDSL1 Trigger Condition | |
| Sequential Trigger Condition | |
| Delta-comparators on read/written data | |
| Reference-Clock (USB-Clock) based Time Stamps | (emulation clock) |
| Time based Trigger Condition | |
| Tick based Time Stamps | |
| Single shot Time Stamps for Time measurement | |
| Stopping XC2000 on Trigger Condition | |
| Emitting Signal on external Break pin on Trigger | |
| Performance counters | |
| Connector | 16-pin standard JTAG Connector |
| UDE-Tool Ordering Code | UDE-XC166/UAD2 and UDE-XC2000 UEC2 |
Embedded Trace
Macrocell ETM Instruction Trace for ARM
The Embedded Trace Macrocell (ETM) of ARM derivatives is used to
capture processor states in real-time using a dedicated connection to
the derivative.UDE supports ETM as 4 bit or 8 bit trace port up to 170 MHz system clock. The program and data trace allows to record up to 1 MSamples. By compiling the trace data directly via the trace hardware this sample rate complies with a multitude of machine code instructions. Each sample is able to contain eight additional external hardware signals. Recording is synchronous to the system clock frequency. This ensures the optimal use of the trace memory and allows application specific time stamps. Start and stop of recording is comfortably controlled via triggers. The total performance of the ETM unit is available for trigger events. The comfortable trace window included in the user interface offers a direct link to the user from trace samples to the related source code, monitoring the runtime of the program based on the time stamps and comprehensive search functions. UDE supports the ETM unit by the Universal Access Device - Trace Board option.
38 Pin ETM High-speed Connector Pod
- Proposed by ARM to support connection to ETM port of ARM systems (LPC21xx and further ARM7, ARM9, ARM11 derivatives)
- Connector system based on 38 pin high-speed connector AMP-MICTOR
- Supports 2,5V to 3,6V I/O ring voltage
Embedded Trace
Macrocell ETB Instruction Trace for ARM
The Embedded Trace Buffer (ETB) extends the ETM unit of ARM derivatives
by an embedded on-chip circular trace buffer. This simplifies the
adaptation of external trace units because the high speed trace
signaling does not need to transfer to the external unit. The trace
buffer is managed and read via the JTAG communication channel.
ETB is supported by UDE with the Philips LPC3000 derivatives.
Nexus Instruction Trace for PowerPC, Power Architecture
UDE supports program trace via the Nexus interface. This function is currently available - in combination with the Universal Access Device 2+ and Universal Access Device 3+ - for the Power Architecture™ derivatives MPC55xx and MPC56xx from Freescale as well as SPC56xx from STMicroelectronics.
A 2-bit, 4-bit or, with the MCUs of the MPC55xx family, even 12-bit wide trace data port with up to 180 MHz clock frequency are supported, whereby up to 1 megasamples can be recorded. With a compression of the trace data direct by the trace hardware, this represents a multiple of machine commands. Moreover, every sample can contain eight additional external hardware signals. Recording of the samples takes place synchronously to the Nexus clock frequency. This enables an optimal use of the trace memory and application optimized timestamps.
Start and stop of the recording can be comfortably controlled via pre-trigger, mid-trigger, post-trigger or address-trigger. The trace window in the user interface offers the developer a direct link from the trace samples to the associated source code, the display of the program runtime on the basis of the timestamps as well as extensive search functions.
Triggered Transfers for XC166, XC2000, XE166, TriCore
The
UDE TTF Recorder uses the Triggered Transfer feature of new Infineon
microcontrollers. Triggered Transfer is part of the on-chip debug
support implemented on these controllers. It allows transferring the
value of a single memory location via the JTAG debug interface.
The transfer is triggered by a debug event of the onchip debug support
(OCDS) unit. There are several types of debug events that can trigger
the transfer depending on the actual type of controller. A typical use
case provided by all supported controller types is to trigger on write
accesses on a single variable and to transfer the new value of the
variable.
The recording is done while the target system is in running state.
Trademarks: ARM, EmbeddedICE, Embedded Trace Macrocell are trademarks of ARM Limited. TriCore is a trademark of Infineon Technologies.