New Methods in Software Test of System-on-Silicon-based Solutions

Lauta, May 2005 - Software verification platforms for SoC based Systems with continued availability over the entire product life cycle are rapidly becoming more important due to increasing complexity and time-to-market constraints. The high demand in terms of flexibility and efficiency however requires a paradigm shift to modular component-based concepts.

System-on-Chip-based solutions are coming on strong but their superior features and benefits are rarely exploited to the full extent possible, for many reasons. Integrated debug functions allow flexible access to complex chip-internal information that should be utilized not only in design but also in production and in the field. This however requires entirely new debug strategies. Also, distribution of software functions over multiple processor cores implies new verification models that take into account testing of the overall functionality and synchronization of each processor's individual software. On top of that, the integration of complete systems into one chip demands capabilities to extend the software test environment to meet upcoming requirements in a modular way. Therefore an open test platform, which allows for later insertion and extension of debug functions, is the indispensable condition for high efficiency. Modern component-based operating systems such as COM, CORBA or NET already provide the appropriate base technology for these strategies.

Infineon's AUDO-NG family shows a good example of how a software design can be inserted within a complex system simulation and test environment. The TC1796 is the first specimen of a new familiy of 32-Bit automotive microcontrollers. It includes two processor kernels, three internal busses, internal RAM and FLASH memory, as well as lots of automotive-specific peripherals. The primary applications for this new breed of silicon-based systems are engine management and control surveillance; applications distinguished by a complex and extremely dynamic processor environment.

In order to make such a complex system testable over its entire product life cycle, it is necessary to design an entirely new concept of an on-chip emulator. It is implemented and manufactured in a special layout version, called the TC1796ED. This consists of the TC1796 plus an Emulator Side Booster (ESB), which includes the functionality of a complete emulator for each of the relevant system-busses - one emulator each for the TriCore and PCP busses plus one emulator each for the two peripheral busses. In addition, there is an integrated logic function that connects events of the four respective emulators and a trace memory.

Of course, the system supports simple debugging mechanisms such as single step operation mode, but the simultaneous tracing of system states is especially critical for more demanding tasks such as software profiling and calibration. Because of limited on-chip trace memory the amount of data must be minimized. Sophisticated mechanisms for trigger signal generation and for trace qualification make sure that trace information were not lost. For this purpose there are a large number of comparators provided for program and data addresses as well as for data itself. The output of these comparators, along with other key signals, are routed to a combinatorial logic block, as well as to event counters and timers. With these tools, very complex interdependencies can be defined as triggers, and state machines can be implemented.

This powerful debug logic requires initializing as many as 500 32-bit registers in preparation for each distinctive analysis task. Such a task requires entirely new approaches and tools for support. pls developed a new approach with three levels of abstraction, to give a maximum degree of freedom in the description of the analysis task while at the same time preserving precise control.

The first level is an assembler-like notation, in which the resources of the emulator hardware can be utilized directly. The language amount of this notation, called "Trace Qualification Language" (TQL), is heavily oriented towards the combinatorial logic of the emulator hardware for generation and evaluation of trigger signals and trace data. The configuration information for the combinatorial connections, which is loaded into the ESB as register content, can be directly generated by assembly of a TQL script.

Here is an example of the applied TQL code:

    tr1evt.data_adr1 = 0xa200045a;
    tr1evt.data_adr2 = 0xa200045b;
    ...
    tr1evt.data_range_read  = false;
    tr1evt.data_range_write = true;
    ...
    tr1evt.code_range_exec = false;
    tr1evt.function = OR;
    signal readdata;
    signal writedata;
    readdata = tr0evt.out;
    writedata = tr1evt.out;
    tsu.prescaler = 1ms;

• Test and measurement tasks can be described in hierarchical order and remain available for reuse as library functions.
• Utilization of the automatic resource administration allows dynamically generated multiple test tasks, as well as automatic loading into the emulator.
• It enables efficient use of complex debug systems without detailed knowledge of the underlying emulation hardware. This is due to the high abstraction level of the new language.

• design and test of systems with distributed intelligence
• powerful and flexible visualization of system states in a complex system
• use of open platforms and new tools to increase program design efficiency
• flexible ability to use existing tools beyond the product design phase, into areas of production, service and maintenance

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