XScale ™ PXA255, PXA27x Derivatives - Architectural Overview of the HighEnd 32-Bit Single-Chip Microcontrollers

Supported Derivatives by Universal Debug Engine

• Marvell/Intel PXA255, PXA270
• Marvell/Intel IXP420, IXP421, IXP422, IXP423, IXP425, IXP455, IXP460, IXP465

XScale ™ Architecture Feature Overview

• 32/16-bit RISC architecture ( ARM v5TE )
• 32-bit ARM V5T instruction set for maximum performance and flexibility
• ARM DSP-Enhanced instruction set and Coprocessor
• Memory Management Unit (MMU)
• enhanced Thumb instruction set for increased code density
• Both big and little endian support
• Unified bus interface, 32-bit data bus carries both instructions and data
• 8-, 16-, and 32-bit Data Types
• Seven-stage pipeline
• 4 GBytes Linear Address Space
• 32-bit ALU and high-performance multiplier, Multiply/Accumulate (MAC)
• Fully static operation
• Memory Management Unit (MMU) with caching support
• High performance features:
  • Instruction and Data cache
  • Various data cache allocation policies which can be configured differently for each application
  • A write buffer
  • Write-back caching
  • Cache locking
  • Branch Target Buffer
• Power Management and Low Power Consumption
• Peripherals: Clock, DMA, LCD, I²C, UART, Real-time clock, PWM, Interrupt

UDE - Universal Debug Engine