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TriCore™ AURIX TC275T Microcontroller - Architectural Overview of the 32-Bit Multi-core Microcontroller with MCDS, DAP2, Aurora (MCA)

AURIX™ is an enormous increase in performance. With Infineon's new 32-bit multicore architecture AURIX™ (AUtomotive Realtime Integrated neXt generation architecture), an extremely high-performance microcontroller (MCU) platform meets the requirements for powertrain and safety applications of the automotive industry.

The first AURIX architecture based MCU, part number TC275T, contains three TriCore processor cores (version 1.6). Two of these are optimized for maximum performance (high-performance TriCore CPU 1.6P) and can execute up to three instructions in one cycle at a maximum clock frequency of 200 MHz. With the third core, a high-efficiency TriCore CPU 1.6E, lowest possible power consumption and an efficient data exchange with the peripherals are the most important factors. It can execute a maximum of one instruction per cycle and is currently clocked at a maximum of 200 MHz. The three TriCore processor cores are connected over a crossbar running at the full CPU speed and avoiding hardware contentions.

The existing TriCore AUDO™ architecture is well-known for a sophisticated On-Chip Debug System (OCDS). This was optimized further for the Aurix family and adapted to the requirements of multicore debugging. With the new Aurix devices, the following interfaces are provided for debug, test and calibration tools: JTAG with up to 40 MHz serial clock, 2-pin and 3-pin Device Access Ports (DAP) as well as a 3-pin DAP2 with up to 160 MHz serial clock. The block transfer rate of the DAP2 could be increased almost three-fold to 30 MByte/s by means of an optimized protocol. The development with associated tool manufacturers such as PLS was supported by suitable hardware tools such as for example the Universal Access Devices (UAD2/UAD3+) family.

TriCore™ TC1130, TC1767ED, TC1797ED, TC1798 Microcontrollers - Architectural Overview of the 32-Bit Microcontroller with MCDS, DAP

TriCore™ is the first single-core 32-bit microcontroller-DSP architecture optimized for real-time embedded systems, made by Infineon. TriCore unifies the best of three worlds — real-time capabilities of microcontrollers, the computational prowess of DSPs, and the highest performance/price implementations of RISC load-store architectures.
The architecture supports a uniform, 32-bit address space, with memory-mapped I/O. It allows for a wide range of implementations, ranging from simple scalar to superscalar. Furthermore, the ISA is capable of interacting with different system architectures, including those with multiprocessing.

To support TriCore implementations with 32-bit instructions and simplified instruction fetching, the entire TriCore architecture is represented in 32-bit instruction formats. In addition, the architecture includes 16-bit instruction formats for the most frequently occurring instructions. These instructions significantly reduce code space, lowering memory requirements, system cost, and power consump-tion. Real-time responsiveness is largely determined by interrupt latency and context-switch time. The high-performance architecture minimizes interrupt latency by avoiding long multicycle instructions and by providing a flexible hardware-supported interrupt scheme. Furthermore, the architecture supports fast context switching.

UDE - Universal Debug Engine with MCDS, Aurora Gigabit Trace, OCDS, DAP, DAP2 Support - Debugger and Emulator for TriCore

UDE - Universal Debug Engine - is a flexible debug and emulator platform with Multi-core debugging. Special feature support

Aurora Gigabit trace (AGBT) support
"IP snooping trace" support
Multi Core Debug Solution (MCDS) by Universal Emulation Configurator (UEC)
On-Chip Debug Support (OCDS L1 and Trace OCDS L2) for Core, PCP, PCP2, DMA
Device Access Port (DAP) support, Device Access Port (DAP2) with 160 MHz serial clock support
Generic Timer Module (GTM) support
Hardware Security Module (HSM) support
Triggered Transfer support
FLASH Memory programming

The UDE demo version within a Starterkit for TriCore is available.

Supported TriCore™ Cores

TriCore™ 1, TriCore™ 1.3, TriCore™ 1.3.1
TriCore™ 1.6 (P,E)

Supported TriCore™ Microcontrollers by Universal Debug Engine

Infineon TriCore TC11IB, TC1100, TC1115, TC1130, TC1161, TC1162, TC1163, TC1164, TC1165, TC1166, TC1167, TC1197
Infineon TriCore TC1724, TC1728
Infineon TriCore TC1736
Infineon TriCore TC1762, TC1765, TC1766, TC1766ED, TC1767, TC1767ED
Infineon TriCore TC1775
Infineon TriCore TC1782, TC1784
Infineon TriCore TC1791, TC1793, TC1796, TC1796ED, TC1797, TC1797ED, TC1798, TC1798ED
Infineon TriCore AUDO-NextGeneration, AUDO-NG, AUDO-Future, AUDO-MAX (AUtomotive unifieD processOr)
Infineon TriCore TC1910, TC1912, TC1920
Infineon TriCore TC275T AURIX (MCA)
Infineon TriCore AURIX (AUtomotive Realtime Integrated neXt generation architecture) (MCA)

TriCore™ Architecture Feature Overview

32-bit architecture
4-GByte unified data, program, and input/output address space
16-/32-bit instructions for reduced code size
Low interrupt latency
Fast automatic context switching
Multiply-accumulate unit
Saturating integer arithmetic
Bit handling
Packed data operations
Zero-overhead loop
Flexible power management
Byte and bit addressing
Little-endian byte ordering
Support for big- and little-endian byte ordering at bus interface
Precise exceptions
Flexible interrupt prioritization scheme

Trademarks: AUDO, AURIX are trademarks of Infineon Technologies. TriCore is a trademark of Infineon Technologies. All other brands or product names are the property of their respective holders.