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C166CBC C161U, SDA6000 Microcontrollers - Architectural Overview of the enhanced 16-Bit Microcontroller

The C161U is a low-cost, high-performance, general-purpose 16-Bit microcontroller that includes USB device interface at full speed of 12 Mbits. The device combines the successful Infineon C166 16-Bit static core technology and offers many on-chip peripheral functions such as USART, 5 timers, Watchdog timer, 8 DMA channels, 8 software configurable bi-directional USB end-points, and a high number of programmable I/Os. C161U's high performance, low cost, and rich peripheral functions provide users the maximum flexibility and performance to implement additional value-added software for product differentiation.

The C165H device combines the successful Infineon C166 16-bit full static core with four independent HDLC controllers, IOM-2 interface and 3kbyte of on-chip Dual-Port RAM. The C165H addresses all embedded HDLC features in ISDN-TA, Intelligent-NT and low cost SOHO-PBX designs offering up to 18 MIPS along with legacy peripherals, such as USART, SSC/SCI and Timers. The C165H device core has a built-in DMA, which provides maximum flexibility and performance. Off-loading the CPU in such a manner allows the user to implement value add software features enabling product differentiation.

The SDA 6000/6001 integrates a high-speed 16-bit C166 microcontroller with digital signal processing for VBI data acquisition and the most flexible display controller ever seen since Megatext. The SDA 6000/6001 is the cost-effective solution for consumer products that require flexible pixel graphics for the optimum user interface:

Television sets with Teletext up to Level 2.5, Electronic Program Guides (NexTView and others), HTML-, GIF-, and JPEG-based applications
Telecommunication devices with gray-scale or color pixel displays
Display-oriented consumer info-devices

UDE - Universal Debug Engine - Debugger and Emulator for C166CBC

UDE - Universal Debug Engine - is a flexible debug platform with Multi-core debugging.

Special feature support:

FLASH Memory programming

Supported C166CBC Microcontrollers by Universal Debug Engine

Infineon C166CBC C161U, C165H, C165UTAH
Infineon C166CBC EGOLD
Mirconas C166CBC SDA6000, SDA6001

Summary of Basic Features of C166CBC

The high flexibility of this architecture allows to serve the diverse and varying needs of different application areas such as automotive, industrial control, or data communications.

Full Static - High Performance 16-Bit CPU With Five-Stage Pipeline

55 ns Instruction Cycle Time at 36 MHz CPU Clock (Single-Cycle Execution)
1-Cycle Multiplication (16 x 16 bit), Background Division (32 / 16 bit) in 21 Cycles
1-Cycle Multiply-and-Accumulate (MAC) Instructions
Enhanced Boolean Bit Manipulation Facilities
Zero-Cycle Jump Execution
Additional Instructions to Support HLL and Operating Systems
Register-Based Design with Multiple Variable Register Banks
Fast Context Switching Support with Two Additional Local Register Banks
2MBytes Total Linear Address Space for Code and Data
1024Bytes On-Chip Special Function Register Area (C166 Family Compatible)
3072Bytes On-Chip Dual-Port SRAM for User Applications
Clock Generation via on-chip PLL (factors 1:0.15 ~ 1:10), or via Prescaler (factors 1:1 ~ 60:1)
Low-Power Management Supporting Idle-, Power-Down- and Sleep-Mode and additional CPU clock slow-down mode with mode control for each peripheral

SDA6000 Features

Powerful 16-bit microcontroller core (compatible to C166 family) running at 33 MHz
Peripherals similar to SAB C161RI (WDT, RTC etc.)
External Memory Interface supporting PC100-type SDRAM (16, 64, or 128 Mbit), EPROM and/or Flash with up to three devices in parallel
New digital slicer with four different programmable data services per VBI field
2D graphic accelerator with DMA facility and hardware support for fast character-drawing
Fully flexible screen refresh unit supporting all display modes from 40x25 characters at 50 Hz up to SVGA 800 x 600 pixels in 64 k colors at 75 Hz progressive scan
Triple 5/6/5-bit RGB DAC with pixel clock up to 50 MHz for analog RGB output
Internal bus/arbitration and buffer system with optimized priorities for maximum throughput and minimum latency of memory access

Control Oriented Instruction Set with High Efficiency

Bit, byte, and word data types
Flexible and efficient addressing modes for high code density
Enhanced boolean bit manipulation with direct addressability of 6 Kbits
for peripheral control and user defined flags
Hardware traps to identify exception conditions during runtime
HLL support for semaphore operations and efficient data access

Integrated On-Chip Memory

3kByte internal RAM for variables, register banks, system stack and code
2kByte on-chip high-speed XRAM for variables, user stack and code (not on all derivatives)

External Bus Interface

Multiplexed or demultiplexed bus configurations
Segmentation capability and chip select signal generation
8-bit or 16-bit data bus
Bus cycle characteristics selectable for four programmable address areas
Up to 2MBytes External Address Space for Code and Data

16-Priority-Level Interrupt System

74 Sources with separate interrupt vectors
Sample-Rate down to 50 ns
Fast external interrupts

8-Channel Peripheral Event Controller (PEC)

Interrupt driven single cycle data transfer
Eliminates overhead of saving and restoring system state for interrupt requests

Intelligent On-Chip Peripheral Subsystems

Up to 56 General Purpose I/O Lines, partly with Selectable Input Thresholds and Hysteresis
Bootstrap loader for flexible system initialization
USB Specification 1.1 Compliant
12Mbps Full-Speed Mode
7SW-configurable Endpoints, in addition to the bi-directional Control Endpoint 0
3 Configurations with 3 alternate settings and 4 interfaces supported
Each non-Control Endpoint can be either Isochronous, Bulk or Interrupt
Autonomous DMA Transfer by on-chip DMA for 8 USB endpoints
On-Chip Debug Support via JTAG Interface

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