C166CBC Derivatives - Architectural Overview of the enhanced 16-Bit CMOS Single-Chip Microcontrollers

• Television sets with Teletext up to Level 2.5, Electronic Program Guides (NexTView and others), HTML-, GIF-, and JPEG-based applications
• Telecommunication devices with gray-scale or color pixel displays
• Display-oriented consumer info-devices

Supported C166CBC Derviatives by Universal Debug Engine

• Infineon C161U
• Infineon C165H
• Infineon C165UTAH
• Infineon EGOLD
• Mirconas SDA6000
• Micronas SDA6001

Summary of Basic Features of C166CBC

Full Static - High Performance 16-Bit CPU With Five-Stage Pipeline

• 55 ns Instruction Cycle Time at 36 MHz CPU Clock (Single-Cycle Execution)
• 1-Cycle Multiplication (16 × 16 bit), Background Division (32 / 16 bit) in 21 Cycles
• 1-Cycle Multiply-and-Accumulate (MAC) Instructions
• Enhanced Boolean Bit Manipulation Facilities
• Zero-Cycle Jump Execution
• Additional Instructions to Support HLL and Operating Systems
• Register-Based Design with Multiple Variable Register Banks
• Fast Context Switching Support with Two Additional Local Register Banks
• 2MBytes Total Linear Address Space for Code and Data
• 1024Bytes On-Chip Special Function Register Area (C166 Family Compatible)
• 3072Bytes On-Chip Dual-Port SRAM for User Applications
• Clock Generation via on-chip PLL (factors 1:0.15 … 1:10), or via Prescaler (factors 1:1 … 60:1)
• Low-Power Management Supporting Idle-, Power-Down- and Sleep-Mode and additional CPU clock slow-down mode with mode control for each peripheral

SDA6000 Features

• Powerful 16-bit microcontroller core (compatible to C166 family) running at 33 MHz
• Peripherals similar to SAB C161RI (WDT, RTC etc.)
• External Memory Interface supporting PC100-type SDRAM (16, 64, or 128 Mbit), EPROM and/or Flash with up to three devices in parallel
• New digital slicer with four different programmable data services per VBI field
• 2D graphic accelerator with DMA facility and hardware support for fast character-drawing
• Fully flexible screen refresh unit supporting all display modes from 40x25 characters at 50 Hz up to SVGA 800 x 600 pixels in 64 k colors at 75 Hz progressive scan
• Triple 5/6/5-bit RGB DAC with pixel clock up to 50 MHz for analog RGB output
• Internal bus/arbitration and buffer system with optimized priorities for maximum throughput and minimum latency of memory access

Control Oriented Instruction Set with High Efficiency

• Bit, byte, and word data types
• Flexible and efficient addressing modes for high code density
• Enhanced boolean bit manipulation with direct addressability of 6 Kbits
• for peripheral control and user defined flags
• Hardware traps to identify exception conditions during runtime
• HLL support for semaphore operations and efficient data access

Integrated On-Chip Memory

• 3kByte internal RAM for variables, register banks, system stack and code
• 2kByte on-chip high-speed XRAM for variables, user stack and code (not on all derivatives)

External Bus Interface

• Multiplexed or demultiplexed bus configurations
• Segmentation capability and chip select signal generation
• 8-bit or 16-bit data bus
• Bus cycle characteristics selectable for four programmable address areas
• Up to 2MBytes External Address Space for Code and Data

16-Priority-Level Interrupt System

• 74 Sources with separate interrupt vectors
• Sample-Rate down to 50 ns
• Fast external interrupts

8-Channel Peripheral Event Controller (PEC)

• Interrupt driven single cycle data transfer
• Eliminates overhead of saving and restoring system state for interrupt requests

Intelligent On-Chip Peripheral Subsystems

• Up to 56 General Purpose I/O Lines, partly with Selectable Input Thresholds and Hysteresis
• Bootstrap loader for flexible system initialization
• USB Specification 1.1 Compliant
• 12Mbps Full-Speed Mode
• 7SW-configurable Endpoints, in addition to the bi-directional Control Endpoint 0
• 3 Configurations with 3 alternate settings and 4 interfaces supported
• Each non-Control Endpoint can be either Isochronous, Bulk or Interrupt
• Autonomous DMA Transfer by on-chip DMA for 8 USB endpoints
• On-Chip Debug Support via JTAG Interface

UDE - Universal Debug Engine

UDE - Universal Debug Engine - is a flexible debug platform with Multi-core debugging. This development workbench is available for Infineon’s 16-bit architecture SAB C16x, C166CBC, C166S V2, the 32-bit TriCore TC1766, TC1796 as well the ST10F16x, ST10F26x and ST10F280 architecture from STMicroelectronics, the ARM7, ARM9, PowerPC and XScale derivatives.

It lets you organize your projects, supports you while building applications and lets you run and test your software in a convenient and cost-efficient way. UDE represents a completely new debugger architecture and tool concept based on a customizable set of standard components and core specific add-ons.

JTAG is fully supported by UDE offering direct high-speed access to the MCUs internal units (registers, control unit...) and features like breakpoints, stepping in ROM/FLASH as well as complex trigger conditions without any external hardware or software resources. OCDS L2 and MCDS instruction trace capability is available for members of the TriCore family. ETM and ETB instruction trace is available for ARM derivatives. Target ROM monitor and Bootstrap loader / RAM monitor solutions for a flexible access via a wide variety of debug channels (ASC, SSC, 3-PIN, CAN) are available.

UDE MemTool as a part of UDE is designed for On-Chip and On-Board FLASH/OTP programming with microcontroller systems using SAB C16x, C166CBC, C166S-V2, XC16x, ST10, TriCore, ARM7, ARM9, PowerPC and XScale derivatives.

The UDE demo version within a Starterkit for C166CBC is available.