XC166 Derivatives ( XC161 , XC164 , XC167 ) - Architectural Overview of the enhanced 16-Bit CMOS Single-Chip Microcontrollers

The Infineon XC161 CJ, XC164 CS and XC167 CI microcontrollers are new derivatives of the popular C166 microcontroller family. Based on the enhanced XC166 architecture they outperform existing 16-bit solutions. The XC166 are an improved and new-generation representative of the Infineon family of the full featured 16-bit single-chip CMOS microcontroller. It combines the extended functionality and performance of the XC166 core with powerful on-chip peripheral subsystems and on-chip Flash memory.

The architecture has been optimized for high instruction throughput and minimum response time to external interrupts. Intelligent peripheral systems have been integrated to reduce the need for CPU intervention. The flexible and intelligent PWM unit simplifies control of AC-, DC- or reluctance motors. A high speed, high resolving ADC handles the fast and accurate translation of complex analog environment. Networked solutions can be confidently solved with powerful communication interfaces like the high speed TwinCAN module with autonomous gateway function.

Supported XC166 Derivatives Universal Debug Engine

• Infineon XC161 CJ
• Infineon XC164 CS
• Infineon XC167 CI

Summary of Basic Features of XC166

High Performance 16-Bit CPU With Five-Stage Pipeline

• 25 ns Instruction Cycle Time at 40 MHz CPU Clock (Single-Cycle Execution)
• 1-Cycle Multiplication (16 × 16 bit), Background Division (32 / 16 bit) in 21 Cycles
• 1-Cycle Multiply-and-Accumulate (MAC) Instructions
• Enhanced Boolean Bit Manipulation Facilities
• Zero-Cycle Jump Execution
• Additional Instructions to Support HLL and Operating Systems
• Register-Based Design with Multiple Variable Register Banks
• Fast Context Switching Support with Two Additional Local Register Banks
• 16MBytes Total Linear Address Space for Code and Data
• 1024Bytes On-Chip Special Function Register Area (C166 Family Compatible)
• Clock Generation via on-chip PLL (factors 1:0.15 … 1:10), or via Prescaler (factors 1:1 … 60:1)

Control Oriented Instruction Set with High Efficiency

• Bit, byte, and word data types
• Flexible and efficient addressing modes for high code density
• Enhanced boolean bit manipulation with direct addressability of 6 Kbits
• for peripheral control and user defined flags
• Hardware traps to identify exception conditions during runtime
• HLL support for semaphore operations and efficient data access

Integrated On-Chip Memory

• 2kBytes On-Chip Dual-Port RAM (DPRAM)
• 4kBytes On-Chip Data SRAM (DSRAM)
• 2kBytes On-Chip Program/Data SRAM (PSRAM)
• 128kBytes On-Chip Program Memory (Flash Memory)

External Bus Interface

• Multiplexed or demultiplexed bus configurations
• Segmentation capability and chip select signal generation
• 8-bit or 16-bit data bus
• Bus cycle characteristics selectable for five programmable address areas
• Up to 16MBytes External Address Space for Code and Data
• Hold- and Hold-Acknowledge Bus Arbitration Support

16-Priority-Level Interrupt System

• 74 Sources with separate interrupt vectors
• Sample-Rate down to 50 ns
• Fast external interrupts

8-Channel Peripheral Event Controller (PEC)

• Interrupt driven single cycle data transfer
• 24-Bit Pointers Cover Total Address Space
• Eliminates overhead of saving and restoring system state for interrupt requests

Intelligent On-Chip Peripheral Subsystems

• Up to 103 General Purpose I/O Lines, partly with Selectable Input Thresholds and Hysteresis
• 12/16-Channel A/D Converter with Programmable Resolution (10-bit or 8-bit) and Conversion Time (down to 2.85 µs)
• Two 16-Channel General Purpose Capture/Compare Units (32 Input/Output Pins)
• Multi-Functional General Purpose Timer Unit with 5 Timers
• Two Asynchronous/Synchronous Serial Channels (USART) with baud rate generator, parity, framing, and overrun error detection
• High Speed Synchronous Serial Channel programmable data length and shift direction
• On-Chip TwinCAN Interface (Rev. 2.0B active) with 32 Message Objects (Full CAN/Basic CAN) on Two CAN Nodes, and Gateway Functionality
• Serial Data Link Module (SDLM), compliant with J1850, supporting Class 2
• IIC Bus Interface (10-bit addressing, 400 kbps) with 3 Channels (multiplexed)
• On-Chip Real Time Clock, Driven by Dedicated Oscillator
• ASC Bootstrap loader for flexible system initialization
• On-Chip Debug Support via JTAG Interface

UDE - Universal Debug Engine

UDE - Universal Debug Engine - is a flexible debug platform with Multi-core debugging. This development workbench is available for Infineon’s 16-bit architecture SAB C16x, C166CBC, C166S V2, the 32-bit TriCore TC1766, TC1796 as well the ST10F16x, ST10F26x and ST10F280 architecture from STMicroelectronics, the ARM7, ARM9, PowerPC and XScale derivatives.

It lets you organize your projects, supports you while building applications and lets you run and test your software in a convenient and cost-efficient way. UDE represents a completely new debugger architecture and tool concept based on a customizable set of standard components and core specific add-ons.

JTAG is fully supported by UDE offering direct high-speed access to the MCUs internal units (registers, control unit...) and features like breakpoints, stepping in ROM/FLASH as well as complex trigger conditions without any external hardware or software resources. OCDS L2 and MCDS instruction trace capability is available for members of the TriCore family. ETM and ETB instruction trace is available for ARM derivatives. Target ROM monitor and Bootstrap loader / RAM monitor solutions for a flexible access via a wide variety of debug channels (ASC, SSC, 3-PIN, CAN) are available.

UDE MemTool as a part of UDE is designed for On-Chip and On-Board FLASH/OTP programming with microcontroller systems using SAB C16x, C166CBC, C166S-V2, XC16x, ST10, TriCore, ARM7, ARM9, PowerPC and XScale derivatives.

The UDE demo version within a Starterkit for XC166 is available.

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