SAB C166 (C161, C163, C164, C165, C166, C167, C16x) Microcontrollers - Architectural Overview of the 16-Bit Microcontroller

The architecture of the Infineon C161, C163, C164, C165, C166, C167, C16x combines the advantages of both RISC and CISC processors in a very well-balanced way. The sum of the features that are combined result in a high-performance microcontroller, which is the right choice not only for today's applications but also for future engineering challenges. The C167CR not only integrates a powerful CPU core and a set of peripheral units into one chip but also connects the units in a very efficient way. One of the four buses used concurrently on the C167CR is the XBUS, an internal representation of the external bus interface. This bus provides a standardized method of integrating application-specific peripherals to produce derivatives of the standard C167.

UDE - Universal Debug Engine

UDE - Universal Debug Engine - is a flexible debug platform with Multi-core debugging.

Special feature support:

FLASH Memory programming

Supported C16x/C166 Microcontrollers by Universal Debug Engine

Infineon SAB C161, C163, C164, C165, C167
Infineon Vecon
Infineon 80C166, 83C166, 88C166

Summary of Basic Features of C161, C163, C164, C165, C166, C167, C16x

The C167CR is an improved representative of the Siemens/Infineon family of full featured 16-bit single-chip CMOS microcontrollers. It combines high CPU performance (up to 12.5 million instructions per second) with high peripheral functionality and modes for power reduction. Several key features contribute to the high performance of the C167CR (the indicated timings refer to a CPU clock speed of 25 MHz).

High Performance 16-Bit CPU With Four-Stage Pipeline

80 ns minimum instruction cycle time, with most instructions executed in 1 cycle
400 ns multiplication (16-bit *16-bit), 800 ns division (32-bit/16-bit)
Multiple high-bandwidth internal data buses
Register based design with multiple variable register banks
Single cycle context switching support
16MBytes linear address space for code and data (von Neumann architecture)
System stack cache support with automatic stack overflow/underflow detection

Control Oriented Instruction Set with High Efficiency

Bit, byte, and word data types
Flexible and efficient addressing modes for high code density
Enhanced boolean bit manipulation with direct addressability of 6 Kbits for peripheral control and user defined flags
Hardware traps to identify exception conditions during runtime
HLL support for semaphore operations and efficient data access

Integrated On-Chip Memory

2kByte internal RAM for variables, register banks, system stack and code
2kByte on-chip high-speed XRAM for variables, user stack and code (not on all derivatives)
128kByte or 32kByte on-chip Program Flash Memory (not for romless devices)

External Bus Interface

Multiplexed or demultiplexed bus configurations
Segmentation capability and chip select signal generation
8-bit or 16-bit data bus
Bus cycle characteristics selectable for five programmable address areas

16-Priority-Level Interrupt System

56 interrupt nodes with separate interrupt vectors
240/400 ns typical/maximum interrupt latency in case of internal program execution
Fast external interrupts

8-Channel Peripheral Event Controller (PEC)

Interrupt driven single cycle data transfer
Transfer count option (standard CPU interrupt after a programmable number of PEC transfers)
Eliminates overhead of saving and restoring system state for interrupt requests

Intelligent On-Chip Peripheral Subsystems

16-Channel 10-bit A/D Converter with programmable conversion time (7.8 ms minimum), auto scan modes, channel injection mode
Two 16-Channel Capture/Compare Units with 2 independent time bases each, very flexible PWM unit/event recording unit with different operating modes, includes four 16-bit Timers/counters, maximum resolution f_CPU /8
4-Channel PWM Unit
Two Multifunctional General Purpose Timer Units GPT1: three 16-bit timers/ counters, maximum resolution f_CPU /8 GPT2: two 16-bit timers/counters, maximum resolution f_CPU /4
Asynchronous/Synchronous Serial Channels (USART) with baud rate generator, parity, framing, and overrun error detection
High Speed Synchronous Serial Channel programmable data length and shift direction
On-Chip CAN Bus Module, Rev. 2.0B active (not on all derivatives)
Watchdog Timer with programmable time intervals
ASC Bootstrap loader for flexible system initialization

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