SuperH™ SH-2A SH7201, SH7250 Microcontrollers - Architectural Overview of the 32-Bit Microcontroller
 The SH-2A processor is a 32-bit RISC processor based on the SuperH™ architecture of Renesas. It has been developed to provide a High-performance CPU core and large-capacity RAM for superior functional products.
UDE - Universal Debug Engine - Debugger and Emulator for SuperH™ SH-2A
UDE - Universal Debug Engine
- is a flexible debug and emulator platform with Multi-core debugging.
Special feature support:
Supported cores
Supported Microcontrollers by Universal Debug Engine
- Renesas SuperH SH-2A SH7201, SH7211, SH7251, SH7254, SH7266, SH7267
SH-2A Architecture Feature Overview
- 32-bit RISC superscalar architecture
- High-performance instruction compatibility with the SH-2 and SH-2E
- Harvard cache architecture
- 5-stage pipeline
- 4 Gbytes Address space
- 15 internal dedicated register banks
- Cache memory
On-chip Peripheral Functions
- FPU (Floating-point unit)
- RAM access-able in a single clock cycle
- DMAC (Direct memory access controller)
- MTU2 (Multifunction timer units)
- A/D and D/A converters
Trademarks: SuperH is a trademark of Renesas Technlogy Corporation. All other brands or product names are the property of their respective holders.
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