ARM11™ (i.MX31) Microcontrollers - Architectural Overview of the 32-Bit Microcontroller (Linux)
The ARM11 ™ embedded microcontroller core is a member of the Advanced RISC Machines (ARM®) family of general purpose 32-bit microprocessors, which offer high performance and very low power consumption. Its outstanding feature is the 16-bit Thumb® subset of the most commonly used 32-bit instructions. These are expanded at run time with no degradation of system performance. This gives 16-bit code density (saving memory area and cost) coupled with 32-bit processor performance.
The ARM architecture is based on Reduced Instruction Set Computer (RISC) principles, and the instruction set and related decode mechanism are much simpler than those of microprogrammed Complex Instruction Set Computers. This simplicity results in a high instruction throughput and impressive real-time interrupt response from a small and cost-effective chip.
Pipelining is employed so that all parts of the processing and memory systems can operate continuously. Typically, while one instruction is being executed, its successor is being decoded, and a third instruction is being fetched from memory.
The ARM memory interface has been designed to allow the performance potential to be realized without incurring high costs in the memory system. Speed-critical control signals are pipelined to allow system control functions to be implemented in standard low-power logic, and these control signals facilitate the exploitation of the fast local access modes offered by industry standard dynamic RAMs.
UDE - Universal Debug Engine with Linux support - Debugger and Emulator for ARM11
UDE - Universal Debug Engine
- is a flexible debug platform with Multi-core debugging.
Special feature support:
Supported ARM cores
Supported Microcontrollers by Universal Debug Engine
Trademarks: ARM, EmbeddedICE and Thumb are registered trademarks of ARM Limited. ARM7, ARM9 and Embedded Trace Macrocell, are trademarks of ARM Limited. All other brands or product names are the property of their respective holders. |
