XE166 (XE164 , XE167) Microcontrollers - Architectural Overview of the enhanced 16-Bit Microcontroller with 32-Bit Performance for Industrial (MCDS, DAP)

The Infineon XE166 microcontrollers are the latest derivatives of the popular C166 microcontroller family. Based on the enhanced XC166 architecture they outperform existing 16-bit solutions with 32-Bit Performance. Operating at 80MHz and one cycle per instruction, XE166 delivers 80MIPS, twice the performance compared with its predecessor XC166 and four times the performance of the fastest classic C166 MCU.
In addition, XE166 offers three times more Flash than XC166 with a maximum Flash capacity of 768 kBytes.

UDE - Universal Debug Engine with MCDS, DAP support - Debugger and Emulator for XE166

UDE - Universal Debug Engine - is a flexible debug and emulator platform with Multi-core debugging.

Special feature support:

• "IP snooping" trace support
  
• Multi Core Debug Solution (MCDS ) support by Universal Emulation Configurator 2 (UEC2)
• XE166ED Emulator
  
• Device Access Port (DAP) support
• Triggered Transfer support
• FLASH Programming support
  

The UDE demo version within a Starterkit for XE166 is available. An XE166 Emulator is available.

Supported XE166 Microcontrollers Universal Debug Engine

• Infineon XE162, XE164, XE167
  

Summary of Basic Features of XE166 for Industrial

High Performance 16/32-Bit CPU With Five-Stage Pipeline

• 12.5 ns Instruction Cycle Time at 80 MHz CPU Clock (Single-Cycle Execution)
• 1-Cycle Multiplication (16 × 16 bit), Background Division (32 / 16 bit) in 21 Cycles
• 1-Cycle Multiply-and-Accumulate (MAC) Instructions
• Enhanced Boolean Bit Manipulation Facilities
• Zero-Cycle Jump Execution
• Additional Instructions to Support HLL and Operating Systems
• Register-Based Design with Multiple Variable Register Banks
• Fast Context Switching Support with Two Additional Local Register Banks
• 16MBytes Total Linear Address Space for Code and Data
• 1024Bytes On-Chip Special Function Register Area (C166 Family Compatible)
• Clock Generation via on-chip PLL, or via Prescaler

Control Oriented Instruction Set with High Efficiency

• Bit, byte, and word data types
• Flexible and efficient addressing modes for high code density
• Enhanced boolean bit manipulation with direct addressability of 6 Kbits
• for peripheral control and user defined flags
• Hardware traps to identify exception conditions during runtime
• HLL support for semaphore operations and efficient data access

Integrated On-Chip Memory

• 1kBytes On-Chip Stand-by RAM (SBRAM)
• 2kBytes On-Chip Dual-Port RAM (DPRAM)
• 16kBytes On-Chip Data SRAM (DSRAM)
• up to 64kBytes On-Chip Program/Data SRAM (PSRAM)
• up to 768kBytes On-Chip Program Memory (Flash Memory)

External Bus Interface

• Single Power Supply from 3.0 V to 5.5 V
• Multiplexed or demultiplexed bus configurations
• Segmentation capability and chip select signal generation
• 8-bit or 16-bit data bus
• Bus cycle characteristics selectable for five programmable address areas
• Up to 16MBytes External Address Space for Code and Data
• Hold- and Hold-Acknowledge Bus Arbitration Support

16-Priority-Level Interrupt System

• 87 Sources with separate interrupt vectors
• Sample-Rate down to 12.5 ns
• Fast external interrupts

8-Channel Peripheral Event Controller (PEC)

• Interrupt driven single cycle data transfer
• 24-Bit Pointers Cover Total Address Space
• Eliminates overhead of saving and restoring system state for interrupt requests

Intelligent On-Chip Peripheral Subsystems

• Up to 118 General Purpose I/O Lines, partly with Selectable Input Thresholds and Hysteresis
• Two Synchronizable 24-Channel A/D Converter with Programmable Resolution (10-bit or 8-bit) and Conversion Time (down to 1.2 µs)
• Four 16-Channel General Purpose Capture/Compare Units (32 Input/Output Pins)
• Multi-Functional General Purpose Timer Unit with 5 Timers
• Two Asynchronous/Synchronous Serial Channels (USART) with baud rate generator, parity, framing, and overrun error detection
• High Speed Synchronous Serial Channel programmable data length and shift direction
• On-Chip MultiCAN Interface (Rev. 2.0B active) with 128 Message Objects (Full CAN/Basic CAN) on Five CAN Nodes and Gateway Functionality
• Six serial interface channels to be used as UART, LIN, buffered SPI, IIC Bus Interface, IIS Interface
• IIC Bus Interface (10-bit addressing, 400 kbps) with 3 Channels (multiplexed)
• On-Chip Real Time Clock, Driven by Dedicated Oscillator
• ASC Bootstrap loader for flexible system initialization
• On-Chip Debug Support via JTAG Interface
• Enhanced power saving modes with flexible power management

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