Embedded Power Architecture™ (PPC440, PPC460, SPC56x, MPC55xx, MPC56xx) Microcontrollers - Architectural Overview of the 32-Bit PowerPC Microcontroller (eTPU, VLE, Nexus, Linux)

UDE - Universal Debug Engine with eTPU, VLE, Nexus, Linux support - PowerPC® - Debugger and Emulator for PowerPC and Power Architecture

UDE - Universal Debug Engine - is a flexible debug and emulator platform with Multi-core debugging for Power Architecture™ and PowerPC®.

Special feature support:

• Time Processor Unit Multi-eTPU support including Byte Crafts eTPU compiler support
• VLE technology support
• Nexus class 3 trace support
• Linux support
• FLASH Memory programming
  

Supported PowerPC Cores

• e200z3 and e200z6 Core
• PowerPC Book E architecture

Supported Power Architecture™ Microcontrollers by Universal Debug Engine

• AMCC PPC440SPe, PPC440EP, PPC440GP, PPC440GR, PPC440SP, PPC460GT
• Freescale™ MPC5514, MPC5516, MPC5517, MPC5533, MPC5534, MPC5553, MPC5554, MPC5561, MPC5565, MPC5566, MPC5567, MPC5568
  
• Freescale™ MPC5510, MPC560xB, MPC560xP, MPC560xS, MPC563xM
• STMicroelectronics SPC560, SPC563
  
• PowerPC e200 Core compatible derivatives

Embedded PowerPC® MPC560x, SPC560, MPC563x, SPC563 Architecture Feature Overview

• Core compatible with the PowerPC Book E architecture using compatible e200 cores
• common variable length encoding (VLE) instruction set
• Frequency range from 32 MHz to 300 MHz
• various core options such as MMU, DSP and floating point extensions
• Multi-master crossbar switch architecture without compromise on performance
• Memory protection unit (MPU)
• large shared automotive IP library (eTPU, Flexray, LinFlex…etc)
• all devices designed for AUTOSAR (AUTomotive Open System ARchitecture)
  

Embedded PowerPC® PPC440SPe Architecture Feature Overview

• Core compatible with the PowerPC Book E architecture
• designed to address high-end embedded applications
• high-performance, low power solution
• on-chip power management features
• configurable 256 kByte sRAM to be used as L2 cache or softwarecontrolled on-chip memory
• DDR-SDRAM and PCI-X interfaces
  
• Gigabit Ethernet interfaces
• GPT (General Purpose Timer)
• PIC (Programable Interrupt Controller)
• serial interfaces UART, II2

Embedded PowerPC® MPC5500 Architecture Feature Overview

• Core compatible with the PowerPC Book E architecture and with the classic PowerPC instruction set
• e200z3 Core
• 4 stage pipeline
• 1 to 2 cycle branch
• 16 bit external Databus, 24 bit Addressbus
  
• 16 MMU entries
• VLE  - Variable length support for high code density
• Harvard architecture
  
• e200z6 Core
• 7 stage pipeline
• 1 to 3 cycle branch
• 32 bit external Databus, 24 bit Addressbus32 MMU entries
• Cache
  
• Unified  intruction/data bus
• on-chip sRAM up to 256 kByte
• on-chip FLASH up to 4 MByte
  
• up to 300 interrupt vectors and 16 priority levels of the INTC (Interrupt controller)
  
• up to 64 eDMA channels
• seriall interfaces eSCI and CAN2.0 FlexCAN,
  
• DSPI (Deserialize/Serialize Peripheral Interface)
• eMIOS (enhanced Modular Timer System)
  
• eTPU (Enhanced Time Processor Unit)
  
• eQADC (enhanced Queued Dual Analog-to-Digital Converter)
• SIU (System Integration Unit)
  
• Nexus class 3+ Support
• PLL and VRC (Voltage Regulator Chip)