| Print |

Embedded PowerPC ™ Derivatives - Architectural Overview of the HighEnd 32-Bit Single-Chip Microcontrollers

Designed specifically to address high-end embedded applications, the PowerPC architecture provides a high-performance, low power solution that interfaces to a wide range of peripherals by incorporating on-chip power management.

Supported PowerPC Cores

e200z3 and e200z6 Core
PowerPC Book E architecture

Supported Derivatives by Universal Debug Engine

AMCC PPC440SPe, PPC440EP, PPC440GP, PPC440GR, PPC440SP
Freescale™ MPC5514, MPC5516, MPC5517, MPC5533, MPC5534, MPC5553, MPC5554, MPC5561, MPC5565, MPC5566, MPC5567
e200 Core compatible derivatives

MPC5200 and further PowerPC families are in preparation.

Embedded PowerPC® PPC440SPe Architecture Feature Overview

Core compatible with the PowerPC Book E architecture
designed to address high-end embedded applications
high-performance, low power solution
on-chip power management features
configurable 256 kByte sRAM to be used as L2 cache or softwarecontrolled on-chip memory
DDR-SDRAM and PCI-X interfaces
Gigabit Ethernet interfaces
GPT (General Purpose Timer)
PIC (Programable Interrupt Controller)
serial interfaces UART, II2

Embedded PowerPC® MPC5500 Architecture Feature Overview

Core compatible with the PowerPC Book E architecture and with the classic PowerPC instruction set
e200z3 Core

4 stage pipeline

1 to 2 cycle branch
16 bit external Databus, 24 bit Addressbus

16 MMU entries
VLE - Variable length support for high code density
Harvard architecture

e200z6 Core

7 stage pipeline
1 to 3 cycle branch
32 bit external Databus, 24 bit Addressbus32 MMU entries
Cache
Unified intruction/data bus

on-chip sRAM up to 256 kByte
on-chip FLASH up to 4 MByte
up to 300 interrupt vectors and 16 priority levels of the INTC (Interrupt controller)
up to 64 eDMA channels
seriall interfaces eSCI and CAN2.0 FlexCAN,
DSPI (Deserialize/Serialize Peripheral Interface)
eMIOS (enhanced Modular Timer System)
eTPU (Enhanced Time Processor Unit)
eQADC (enhanced Queued Dual Analog-to-Digital Converter)
SIU (System Integration Unit)
Nexus class 3+ Support
PLL and VRC (Voltage Regulator Chip)

UDE - Universal Debug Engine

UDE - Universal Debug Engine - is a flexible debug platform with Multi-core debugging. This development workbench is available for Infineon’s 16-bit architecture SAB C16x, C166CBC, C166S V2, the 32-bit TriCore TC1766, TC1796 as well the ST10F16x, ST10F26x and ST10F280 architecture from STMicroelectronics, the ARM7, ARM9, PowerPC and XScale derivatives.

It lets you organize your projects, supports you while building applications and lets you run and test your software in a convenient and cost-efficient way. UDE represents a completely new debugger architecture and tool concept based on a customizable set of standard components and core specific add-ons.

JTAG is fully supported by UDE offering direct high-speed access to the MCUs internal units (registers, control unit...) and features like breakpoints, stepping in ROM/FLASH as well as complex trigger conditions without any external hardware or software resources. OCDS L2 and MCDS instruction trace capability is available for all member of the TriCore family. ETM and ETB instruction trace is available for ARM derivatives. Target ROM monitor and Bootstrap loader / RAM monitor solutions for a flexible access via a wide variety of debug channels (ASC, SSC, 3-PIN, CAN) are available.

UDE MemTool as a part of UDE is designed for On-Chip and On-Board FLASH/OTP programming with microcontroller systems using SAB C16x, C166CBC, C166S-V2, XC16x, ST10, TriCore, ARM7, ARM9, PowerPC and XScale derivatives.

Trademarks

Freescale is a trademark of Freescale Semiconductor, Inc. PowerPC is a trademark of IBM Corporation. All other brands or product names are the property of their respective holders.