XC2000 XC2287, XC2367, XC2786 Microcontrollers - Architectural Overview of the enhanced 16-Bit Microcontroller with 32-Bit Performance for Automotive (MCDS, DAP)

The Infineon XC2267, XC2264, XC2287, XC2286 and XC2285 microcontrollers are latest derivatives of the popular C166 microcontroller family. Based on the enhanced C166S V2 architecture they outperform existing 16-bit solutions with 32-Bit Performance. It combines the extended functionality and performance of the C166S V2 Core with powerful on-chip peripheral subsystems and on-chip Flash memory.

The architecture has been optimized for high instruction throughput and minimum response time to external interrupts. Intelligent peripheral systems have been integrated to reduce the need for CPU intervention. The flexible and intelligent PWM unit simplifies control of AC-, DC- or reluctance motors. A high speed, high resolving ADC handles the fast and accurate translation of complex analog environment. Networked solutions can be confidently solved with powerful communication interfaces like the high speed TwinCAN module with autonomous gateway function.

UDE - Universal Debug Engine with MCDS, DAP support - Debugger and Emulator for XC2000

UDE - Universal Debug Engine - is a flexible debug and emulator platform with Multi-core debugging.

Special feature support:

• "IP snooping" trace support
  
• Multi Core Debug Solution (MCDS ) support by Universal Emulation Configurator 2 (UEC2)
  
• XC2000ED Emulator
  
• Device Access Port (DAP) support
• Triggered Transfer support
• FLASH Memory programming 

The UDE demo version within a Starterkit for XC2000 is available. A XC2000ED Emulator is available.

Supported XC2200, XC2300, XC2700 Microcontrollers by Universal Debug Engine

• Infineon XC2000 XC2264, XC2267, XC2268, XC2269, XC2285, XC2286, XC2287, XC2288, XC2289 (XC2200 Body)
• Infineon XC2000 XC2200H, XC2200I, XC2200L, XC2200M, XC2200N, XC2200U
• Infineon XC2000 XC2310, XC2320, XC2365, XC2387 (XC2300 Safety)
• Infineon XC2000 XC2300A, XC2300B, XC2300C, XC2300D, XC2300E, XC2300S
• Infineon XC2000 XC2766, XC2786 (XC2700 Powertrain)
  
• Infineon XC2000 XC2700S
  

Summary of Basic Features of XC2000 for Automotive

High Performance 16/32-Bit CPU With Five-Stage Pipeline

• 12.5 ns Instruction Cycle Time at 80 MHz CPU Clock (Single-Cycle Execution)
• 1-Cycle Multiplication (16 × 16 bit), Background Division (32 / 16 bit) in 21 Cycles
• 1-Cycle Multiply-and-Accumulate (MAC) Instructions
• Enhanced Boolean Bit Manipulation Facilities
• Zero-Cycle Jump Execution
• Additional Instructions to Support HLL and Operating Systems
• Register-Based Design with Multiple Variable Register Banks
• Fast Context Switching Support with Two Additional Local Register Banks
• 16MBytes Total Linear Address Space for Code and Data
• 1024Bytes On-Chip Special Function Register Area (C166 Family Compatible)
• Clock Generation via on-chip PLL, or via Prescaler

Control Oriented Instruction Set with High Efficiency

• Bit, byte, and word data types
• Flexible and efficient addressing modes for high code density
• Enhanced boolean bit manipulation with direct addressability of 6 Kbits
• for peripheral control and user defined flags
• Hardware traps to identify exception conditions during runtime
• HLL support for semaphore operations and efficient data access

Integrated On-Chip Memory

• 1kBytes On-Chip Stand-by RAM (SBRAM)
• 2kBytes On-Chip Dual-Port RAM (DPRAM)
• 16kBytes On-Chip Data SRAM (DSRAM)
• up to 64kBytes On-Chip Program/Data SRAM (PSRAM)
• up to 768kBytes On-Chip Program Memory (Flash Memory)

External Bus Interface

• Multiplexed or demultiplexed bus configurations
• Segmentation capability and chip select signal generation
• 8-bit or 16-bit data bus
• Bus cycle characteristics selectable for five programmable address areas
• Up to 16MBytes External Address Space for Code and Data
• Hold- and Hold-Acknowledge Bus Arbitration Support

16-Priority-Level Interrupt System

• 87 Sources with separate interrupt vectors
• Sample-Rate down to 12.5 ns
• Fast external interrupts

8-Channel Peripheral Event Controller (PEC)

• Interrupt driven single cycle data transfer
• 24-Bit Pointers Cover Total Address Space
• Eliminates overhead of saving and restoring system state for interrupt requests

Intelligent On-Chip Peripheral Subsystems

• Up to 118 General Purpose I/O Lines, partly with Selectable Input Thresholds and Hysteresis
• 24-Channel A/D Converter with Programmable Resolution (10-bit or 8-bit) and Conversion Time (down to 1.2 µs)
• Four 16-Channel General Purpose Capture/Compare Units (32 Input/Output Pins)
• Multi-Functional General Purpose Timer Unit with 5 Timers
• Two Asynchronous/Synchronous Serial Channels (USART) with baud rate generator, parity, framing, and overrun error detection
• High Speed Synchronous Serial Channel programmable data length and shift direction
• On-Chip MultiCAN Interface (Rev. 2.0B active) with 128 Message Objects (Full CAN/Basic CAN) on Five CAN Nodes and Gateway Functionality
• Six serial interface channels to be used as UART, LIN, buffered SPI, IIC Bus Interface, IIS Interface
• IIC Bus Interface (10-bit addressing, 400 kbps) with 3 Channels (multiplexed)
• On-Chip Real Time Clock, Driven by Dedicated Oscillator
• ASC Bootstrap loader for flexible system initialization
• On-Chip Debug Support via JTAG Interface
• Enhanced power saving modes with flexible power management